Browse Prior Art Database

Logic Book Implantation

IP.com Disclosure Number: IPCOM000104221D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 2 page(s) / 24K

Publishing Venue

IBM

Related People

Loehlein, WD: AUTHOR [+4]

Abstract

The problem of RC delays on chip global nets is remedied by distributing the logic driving such nets. Logic books are implanted into the body of an embedded array such that a line routed across the array is separated into sections which interconnect the logic books. As the wire delay is quadratically dependent upon the wire length, the overall line delay is thus reduced.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Logic Book Implantation

      The problem of RC delays on chip global nets is remedied by
distributing the logic driving such nets.  Logic books are implanted
into the body of an embedded array such that a line routed across the
array is separated into sections which interconnect the logic books.
As the wire delay is quadratically dependent upon the wire length,
the overall line delay is thus reduced.

      The implantation of logic books into the array body is made pos
sible by an amorphous array structure that is porous for logic book
penetration.  The figure shows an ideal distribution of logic areas
inside a macro, such as an array.  For practical reasons, the areas
allowing logic implantations are limited and positioned at the best
strategic places inside the array dependent upon its size and
outline.