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Use of the L2 Directory in Multiprocessor Designs

IP.com Disclosure Number: IPCOM000104229D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 2 page(s) / 100K

Publishing Venue

IBM

Related People

Pomerene, J: AUTHOR [+2]

Abstract

The presence of an L2 affects the entire nature of a multiprocessor design in a fundamental way. A special aspect of this is the directory of the L2 that provided complementary information that can reduce the impact of the cache miss penalty and the frequency of cache misses. The point of a configuration of 16 processors each with their own L1-caches operating off a single logical L2 provides for specific improvements in the overall design as well as new perspective on how the processor's work should be organized and managed. One way of accomplishing this is to derive the true pattern of cache usage by using aspects associated with the L2.

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Use of the L2 Directory in Multiprocessor Designs

      The  presence  of  an  L2  affects  the  entire  nature of a
multiprocessor design in a fundamental way.  A special aspect of
this  is  the  directory  of  the   L2   that   provided
complementary  information that can reduce the impact of the cache
miss penalty and the frequency of  cache  misses.  The point  of  a
configuration of 16 processors each with their own L1-caches
operating off a single logical L2 provides for specific improvements
in the overall design as well  as  new perspective  on how the
processor's work should be organized and managed.  One way of
accomplishing this is to derive the true pattern of cache usage by
using aspects associated with the L2.   This pattern can then  be
tested  by  making  the anticipated  omissions  that  occur
subsequently,  if  such omissions are commensurate with the L1  cache
status.  This process is called DAMPING CACHE DYNAMICS.

      Historically, the use of an L2 in the cache hierarchy has
presented the opportunity of reducing the  impact  of  L3 misses.
The  L2 serves, in a recursive fashion, the role of providing for a
faster mode of access to the lines that are not present in the L1.

      It  should  be  recognized  that  the  L2  is  more  than  a
repository of data that can be accessed more quickly.  The L2 has a
directory and this an aspect of the L2 is by far much more valuable
as the directory of the L2 offers opportunity for improvements in the
operation of the L1 cache.  For example, the directory of the L2,
independent of the data, can provide for a simple means of
redistributing cache lines from "hot" congruence classes to
congruence classes that are  under-utilized  and thereby reduce cache
misses.   This is done in  conjunction  with  a TABLE that allows a
means of direct access to the relevant L1-cache directory and
L1-cache array positions associated  with  the processor  access.
The Table that directly specifies the location within the cache
directory and cache arrays of the information  and data that is being
accessed can be accessed based on the virtual address used by the
processor.  Such  a table is called a ECCDTAT and manages itself
based on its own misses.  A  miss for the ECCDTAT is based on an
incorrect comparison between the output of the DLAT and the cache
directory entry retrieved by using the ECCDTAT.  Such a table can be
the basis of arbitrary placement of cache lines based on  congruence
class  usage  and  the  resolution  of table collisions can be
resolved by incorporating the "chosen" congruence class in the L2
directory entry.

      The  directory  of the L2 can become the focus of the system
and the operations of the entire memory hierarchy  that  can actively
be coordinated by this resource.  Imagine a system which has 16
processors and each processor has an L1 cache  structure.  All L1
cach...