Browse Prior Art Database

Performance Improvement of Multi-Directional Bus through a Repower or Hub

IP.com Disclosure Number: IPCOM000104234D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 4 page(s) / 78K

Publishing Venue

IBM

Related People

Fuhs, RE: AUTHOR [+3]

Abstract

A method of improving performance of a bus which contains one or more repower blocks or hubs is disclosed.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Performance Improvement of Multi-Directional Bus through a Repower or Hub

      A method of improving performance of a bus which contains one
or more repower blocks or hubs is disclosed.

      A unique bus tag line and its use is described which allows for
improved performance of a repowered bus.  This bus tag line will be
called NEXT tag in this disclosure.  The NEXT tag would be driven by
the bus unit which was 'next-in-line' to drive the bus and received
by the repower (Figs. 1 and 2).

      The NEXT tag would be activated by a bus unit as soon as it
realized that it was to be the next bus owner.  Thus, it would drive
its tag active even though another bus units command may still be on
the bus.

      The NEXT tag would be de-activated by the bus unit as it
initiated its command (as it began driving the bus).

      With this implementation, there will never be two bus units
trying to drive this signal simultaneously.

      The repower logic would sample all the NEXT tags at the
conclusion of every command (and during any bus idle period).  It
would then set the appropriate driver enable latches in advance of an
incoming command, thus saving a cycle of delay on every command.

      Fig. 3 shows a timing diagram of two command transfers
(transfer A and transfer B) in a system with no 'NEXT' signal.  The
commands' source and destination are on different 'sides' of the
repower.  It takes two cycles for a command from device A to arrive
at device B (and vice-versa).

      Fig. 4 shows a timing diagram of the same command transfers in
a system with a 'NEXT' signal.  It takes only one cycle for a command
from device A to arrive at device B (and vice-versa).

o   Bus Unit 'A' has been gran...