Browse Prior Art Database

Memory Expansion Card Parity with an Error Correction Code Switch

IP.com Disclosure Number: IPCOM000104235D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 4 page(s) / 129K

Publishing Venue

IBM

Related People

Bush, H: AUTHOR [+4]

Abstract

In a memory adaptor card, suitable for use in an IBM PS/2* personal computer, if a hard error is detected, an error correction code (ECC) switch is activated only during this error situation to maintain performance, thus, the card is replaced only when two or more hard errors occur on the card. The ECC runs concurrently with normal operations, thus allowing default cycle reads from the memory expansion card. If an error is detected, however, the ECC control scrubs the bad memory location with corrected data and notifies the system with an interrupt that a correctable error had occurred.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Memory Expansion Card Parity with an Error Correction Code Switch

      In a memory adaptor card, suitable for use in an IBM PS/2*
personal computer, if a hard error is detected, an error correction
code (ECC) switch is activated only during this error situation to
maintain performance, thus, the card is replaced only when two or
more hard errors occur on the card.  The ECC runs concurrently with
normal operations, thus allowing default cycle reads from the memory
expansion card.  If an error is detected, however, the ECC control
scrubs the bad memory location with corrected data and notifies the
system with an interrupt that a correctable error had occurred.

      Previously, when a user of an IBM PS/2 personal computer
encountered a hard parity error, the only method of recovery was to
re-boot or power-down.  The ECC switch allows data to be corrected in
memory so that hard single errors are eliminated.  If the adaptor
card is encountering too many errors, the card is switched into a
degraded mode, which forces ECC to be on all the time.  This allows
an adaptor card with a bad bit location to be used until a
replacement card can be obtained for reduced down time.

      The memory expansion card parity with the error correction code
includes three major sections, (1) an expansion memory which can be
any bit length in width depending on the users needs and purpose, (2)
an ECC memory, the size of which is directly related to how many bits
the user has decided to make the expansion memory, i.e., from 5 bits
wide of ECC memory for 8 bits wide of expansion memory to 8 bits wide
of ECC memory for 64 bits wide of expansion memory, and (3) a MICRO
CHANNEL*/adaptor control (MCAC) which includes both ECC
generation/checking and a memory controller.  The relationship
between the MICRO CHANNEL/adaptor control (MCAC) and the expansion
and ECC memories is indicated in Fig. 1.

      The MCAC is illustrated in more detail in Fig. 2.  The
description of the MCAC will be considered as if the memory is only
one byte wide, for simplicity purposes, but this principle can be
applied to any width of memory that is required.

      The read operation, as indicated in the graphs of Fig. 3,
without the error, is as follows:

1.  The MICRO CHANNEL bus master (MCBM) drives the adaptor card
    address lines active on the bus.

2.  The memory expansion card (MEC) drives data size, DS, lines
    active.

3.  The MCBM drives status lines, S0 and S1, to their valid states.
    In this case S1 is low and S0 is high, reflecting a read
    operation.  The MEC then begins a memory read operation.

4.  The MCBM drives the address latch (ADL) line active low followed
    by the command (CMD) line active low.  5) The MCBM then drives
    ADL line inactive high followed by driving the status lines
    inactive high.  6) The MEC then proceeds with the read and
    present the da...