Browse Prior Art Database

Digitally Synthesized Bit Jitter Generator

IP.com Disclosure Number: IPCOM000104242D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 1 page(s) / 23K

Publishing Venue

IBM

Related People

Armstrong, DR: AUTHOR

Abstract

Disclosed is a means of generating and controlling jitter for a serial data signal. This solution provides a repeatable circuit that does not require adjustment (which was previously needed to allow for variations in analog implementations). It also provides more accurate control of the phase shifting which is necessary for parametric testing of devices. This circuit is currently being used to test diskette controller devic- es.

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Digitally Synthesized Bit Jitter Generator

      Disclosed is a means of generating and controlling jitter for a
serial data signal.  This solution provides a repeatable circuit that
does not require adjustment (which was previously needed to allow for
variations in analog implementations).  It also provides more
accurate control of the phase shifting which is necessary for
parametric testing of devices.  This circuit is currently being used
to test diskette controller devic- es.

      This logic allows the jitter clock to be programmably phase
shifted by dividing a reference clock by the input data with a
counter.  The input data loaded into the counter determines the
length of the jitter clock pulse in the corresponding number of
reference clock cycles.  This input data can be kept constant to
produce a desired frequency or varied to provide for phase shifting
and bit jitter capability.

Disclosed Anonymously.