Browse Prior Art Database

Control Circuit for Loading a Counter with an Asynchronous Pulse

IP.com Disclosure Number: IPCOM000104252D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 1 page(s) / 40K

Publishing Venue

IBM

Related People

Stine, E: AUTHOR

Abstract

Disclosed is a circuit for causing a counter to be loaded upon the occurrence of an asynchronous pulse without violating the setup and hold times of the counter and without delaying or extending the load time more than necessary.

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Control Circuit for Loading a Counter with an Asynchronous Pulse

      Disclosed is a circuit for causing a counter to be loaded upon
the occurrence of an asynchronous pulse without violating the setup
and hold times of the counter and without delaying or extending the
load time more than necessary.

      As shown in the figure, an asynchronous pulse, the ASYNCH LOAD
signal, is applied as an input to an OR gate 1 and as a data input to
set a pair of flip-flops 2 and 3.  The CLOCK signal is applied as a
clock input to flip-flop 3 and to a counter 4.  An inverter 5 is used
to invert the CLOCK signal for application as a clock input to
flip-flop 2.  The outputs of both flip-flops 2 and 3 are applied as
inputs to OR gate 1, and the output of this gate is applied as the
asynch load input of counter 4.

      Thus, OR gate 1 allows the ASYNCH LOAD signal to start loading
the counter.  Flip-flops 2 and 3 sample this signal on both edges of
the CLOCK signal, extending the asynch load input of counter 4 by, at
most, one clock period for synchronization.  At the end of the ASYNCH
LOAD signal, each flip-flop 2 and 3 is reset with its clock input.
In this way, an ASYNCH LOAD signal as short as half the clock period
can be recognized and used to load the counter.

      Flip-flops 2 and 3 are of a metastable immune type, which does
not become metastable if setup and hold times are violated.  Instead,
under such conditions of violation, flip-flops 2 and 3 increase...