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Scannable Routing Method for Single-Latch Register Array

IP.com Disclosure Number: IPCOM000104254D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 1 page(s) / 32K

Publishing Venue

IBM

Related People

Conor, SM: AUTHOR [+4]

Abstract

This new register array design method results in much less test time, greater array density, and reduced word and bit line capacitance while preserving test capability of a standard method which uses a level sensitive scan design (LSSD) L1/L2 latch as its memory cell. The new method omits the L2 latch in the cell and each bit of the array becomes either a single L1 or L2* latch.

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This is the abbreviated version, containing approximately 100% of the total text.

Scannable Routing Method for Single-Latch Register Array

      This new register array design method results in much less test
time, greater array density, and reduced word and bit line
capacitance while preserving test capability of a standard method
which uses a level sensitive scan design (LSSD) L1/L2 latch as its
memory cell.  The new method omits the L2 latch in the cell and each
bit of the array becomes either a single L1 or L2* latch.

      The figure shows one scan chain connection or routing to
implement the new method in a 4x4 array.  The memory array is
arranged into L1 and L2* columns alternately.  Two scan chains,
SCANIN1 and SCANIN2 are used to propogate data through the array.
SCANIN1 starts from the top left cell (L1), connects the L2* at row

2, column 2 (2,2) forming the first LSSD latch.  The second one is
formed between L1 (1,3) and L2* (2,4), etc., as shown.  This array
structure guarantees that the L1 and L2* of every  shift register
latch (SRL) are independent of each other in terms of word line and
bit line, i.e., they must not be on the same row or column.  Thus,
standard testing capability of the older, standard design is
preserved.

Disclosed Anonymously.