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An EEPROM Cell with Asymetrical Sidewall to Minimize Drain Couplings

IP.com Disclosure Number: IPCOM000104309D
Original Publication Date: 1993-Apr-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 80K

Publishing Venue

IBM

Related People

Acovic, A: AUTHOR [+2]

Abstract

An EEPROM cell with asymetrical sidewall to reduce drain to floating gate coupling is presented, so that the enhanced short channel effect and the drain disturb are minimized. This approach allows to manufacture sub quarter micron EEPROMS.

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An EEPROM Cell with Asymetrical Sidewall to Minimize Drain Couplings

      An EEPROM cell with asymetrical sidewall to reduce drain to
floating gate coupling is presented, so  that  the  enhanced short
channel  effect  and the drain disturb are minimized.  This approach
allows to  manufacture  sub  quarter  micron EEPROMS.

      In  the  EEPROM  cell, using tunneling from the floating gate
to the control gate as the erase mechanism (an  example of such a
cell is the EEPROM using Single Electron Injectors with  Silicon
Rich  Oxide [1]), a higher electric field is required between the
control gate and the floating gate than the  field  between  the
floating  gate  and  the   silicon substrate.  This  is  necessary
to avoid tunneling from the floating gate to the substrate.   Simple
capacitive  divider consideration   indicate   that  this
necessitates  a  much stronger coupling  of  the  floating  gate  to
the  silicon substrate  than  to  the control gate (C sub FG/B > C
sub FG/CG) (Fig.  1).  This, however, leads to the appearance of a
pseudo  short channel  effect due to the coupling of the drain
junction to the floating gate (Fig. 1), and thus increases the
off-state current, which imposes a limit  on  miniaturization  of
the EEPROM  cell.    This  phenomenon becomes more severe as the
ratio L sub 'GB overlap'/L sub 'eff' increases, where L sub 'GB
overlap'  is  the gate to substrate overlap length and L sub 'eff' is
the effective channel length of the device (Fig. 2).

      The use of an asymetrical sidewall on the drain side of the
MOSFET is proposed to minimize the overlap between the highly doped
drain and the floating  gate  (Fig. 3).  The sp...