Browse Prior Art Database

Processor Controller Critical Data Access Across System Power Off

IP.com Disclosure Number: IPCOM000104310D
Original Publication Date: 1993-Apr-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 172K

Publishing Venue

IBM

Related People

Charaf, M: AUTHOR [+3]

Abstract

Disclosed is a technique that allows for the access of critical data on DASD in a duplexed system when one side of that system is powered off, thus rendering the DASD--and the data--on that side unavailable. This technique is applied to the duplexed Processor Controller Element (PCE) of certain Multiprocessor (MP) models of the IBM Enterprise Systems/9000* (ES/9000) family of processors and is a combination of changes in several Licensed Internal Code (LIC) components with

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Processor Controller Critical Data Access Across System Power Off

      Disclosed is a technique that allows for the access of critical
data on DASD in a duplexed system when one side of that system is
powered off, thus rendering the DASD--and the data--on that side
unavailable.  This technique is applied to the duplexed Processor
Controller Element (PCE) of certain Multiprocessor (MP) models of the
IBM Enterprise Systems/9000* (ES/9000) family of processors and is a
combination of changes in several Licensed Internal Code (LIC)
components with

1.  New Unit Support Interface (USI)-bus commands over a four-wire,
    asynchronous, serial interface;
2.  An I/O-like operation to transmit data;
3.  Algorithms on where to read/write the critical data from/to;
4.  An algorithm to determine which data-transfer method to use.

      In a duplexed PCE environment, multiple bytes of critical data
used to determine System and PCE configurations are kept on both PCE
sides' DASD.  This information is read from both PCE sides' DASD, and
via comparisons and checks, the Processor Controller initializes
itself so that the Processor Complex powers up in the correct System
configuration: Single Image (SI) or Physically Partitioned (PP).  In
addition, access to the other side's DASD is needed to avoid a PCE
condition known as two-sides-down.  Because of data loss or
down-level data since a PCE side is/was not powered, the initializing
PCE can render itself and the other PCE side (if powered) into an
offline state, leaving the Processor Complex with no Processor
Controller.

      In order to compensate for the inability to access the remote
PCE side's DASD when the remote side is powered off, another
non-volatile area within the PCE is needed to keep this critical
data.  Random Access Memory (RAM) in the respective Initial Power
Controller (IPC) of each PCE handles this requirement because, except
for the loss of Alternating Current (AC) input power, RAM is always
available.  Fig. 1 shows the relationship between the two PCE sides,
the main data paths, and the three major components--IPC, PAP,
IOSP--of this duplexed system.

      The capability to store and retrieve critical data in the RAMs
of the IPCs of the PCE is implemented through new Unit Support
Interface (USI)-bus commands, "Write Local Or Remote Critical Data"
and "Read Local Or Remote Critical Data".  The write/read local
critical data operations on each PCE are similar to existing
write/read IPC RAM operations, while the write/read remote operations
utilize the four-wire, asynchronous, serial interface between the
IPCs in duplexed PCEs.

      The IPC-to-IPC interface normally is used to continually
transmit two-byte (7 data bits, 1 parity bit each) groups of status
and request information from one IPC to the other.  However, because
of the time involved in serial transmission of the multiple two-byte
groups required for the new remote data commands, these commands...