Browse Prior Art Database

Dual Frame Buffer Interleaving

IP.com Disclosure Number: IPCOM000104311D
Original Publication Date: 1993-Apr-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 6 page(s) / 186K

Publishing Venue

IBM

Related People

Aranda, M: AUTHOR [+2]

Abstract

VRAM bandwidth has not kept pace with density increases. Twenty 1-Megabit VRAMs (256k x 4) are sufficient for an 8-bit plane double buffered frame buffer for a 1280 x 1024 screen. Organization of these 20 VRAMs to maximize drawing bandwidth is particularly challenging when faced with the constraints imposed by windows. One particular constraint is that data from both frame buffers must be available for selection on a per pixel basis as different windows are displayed.

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Dual Frame Buffer Interleaving

      VRAM bandwidth has not kept pace with density increases.
Twenty 1-Megabit VRAMs (256k x 4) are sufficient for an 8-bit plane
double buffered frame buffer for a 1280 x 1024 screen.  Organization
of these 20 VRAMs to maximize drawing bandwidth is particularly
challenging when faced with the constraints imposed by windows.  One
particular constraint is that data from both frame buffers must be
available for selection on a per pixel basis as different windows are
displayed.

      This article presents an architecture that optimizes drawing
bandwidth to the VRAMs while supporting window IDs including
independent frame buffer selection on a per window (implies per
pixel) basis.

      In graphics systems the pixels (here a pixel, picture element,
refers to each dot or color triad on a display screen) of a display
are each represented by a value in a memory.  This memory
representation of a display is referred to as a Frame Buffer.  For a
high resolution display there are 1280 x 1024 or 1,310,720 pixels.
Each pixel can be represented by 1-24 or more bits for the color or
base planes and 1-4 or more bits for overlay planes.  A plane is
defined as the number of pixels on a screen by 1 bit deep.  For
example, a frame buffer might have 8 or 24 color planes and 4 overlay
planes.  The frame buffer actually has twice the number color and
overlay planes to support the technique of double buffering.  Double
buffering is the technique of rendering to one set of planes, e.g.,
frame buffer A, while the other set of planes (frame buffer B) is
being displayed.  Double buffering provides very clean image
transition.

      One other feature of high performance graphics systems is the
use of another set of bit planes to partition the screen into
windows.  Windows are independent portions of the screen that each
represent an application.  Each window is assigned an ED number that
is drawn into the window planes to define the boundaries of the
window.  As each application is drawn to the color planes the window
ID associated with the application defines the area where the
application can be drawn.  See Fig. 1 for an example.

      The window ID value is also used to index into a lookup table
where the display frame buffer value A or B and a color table
selection value can be stored.

      The 1 meg VRAMs the internal array is organized as 512 rows x
512 columns by 4 bits deep.  The number of VRAMs that map to a 1280 x
1024 screen is (1280x1024)/(512x512) = 5.  Five VRAMs yield a single
buffered 4 bit deep 1280 x 1024 frame buffer.  To get 8 bit or deeper
pixels, VRAMs are stacked 5 wide by 2 to n deep.  For a double frame
buffer system, a second group of 5 x n VRAMs is added.  If separate
frame buffers are put in separate VRAMs, the maximum number of pixels
that can be parallelized is five (Fig. 2).

      If, however, both frame buffers are interleaved on both groups
of VRAMs, the...