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Browse Prior Art Database

Closest-to-Completion Logic to Store Finished Program Exception Codes

IP.com Disclosure Number: IPCOM000104321D
Original Publication Date: 1993-Apr-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 79K

Publishing Venue

IBM

Related People

Chou, N: AUTHOR [+6]

Abstract

Disclosed is a method by which program exception codes can be economically stored until instruction completion time. Traditional methods for out of sequence execution have placed program exception information into a finish array. In a machine with a large number of instruction IDs (IIDs) and potential program exceptions, the finish array would be too large.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Closest-to-Completion Logic to Store Finished Program Exception Codes

      Disclosed is a method by which program exception codes can be
economically stored until instruction completion time.  Traditional
methods for out of sequence execution have placed program exception
information into a finish array.  In a machine with a large number of
instruction IDs (IIDs) and potential program exceptions, the finish
array would be too large.

      IIDs with exceptions are compared to each other and to
exception IIDs already stored, if any.  The IID that is most nearly
current, i.e., closest to completion, is kept.  Any others are NOT
stored.  Hence, only one register is required to store the exception
and its IID.  If no exception was stored, the first exception
reported gets stored.  Fig. 1 illustrates an example of closest to
completion hardware.  Of special interest are the comparators with
the '<' symbol.  These comparators are like less than comparators but
are modified to take into account an extra bit in the IID called a
wrap bit.  The high order bit of the IID (bit 0, or the leftmost bit)
is defined as the wrap bit.  If N is the number of IIDs which can be
active in the processor, then the instruction decode logic assigns N
+ 1 bit wide IIDs via an N + 1 counter.  The purpose of this wrap bit
is to cut in half the number of comparators required for the closest
to completion logic.  Fig. 2 helps show how this savings is achieved
for a machine which has a maximum of 32 acti...