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Self-Synchronizer for Self-Resetting Complementary Metal Oxide Semiconductor Circuits

IP.com Disclosure Number: IPCOM000104332D
Original Publication Date: 1993-Apr-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 103K

Publishing Venue

IBM

Related People

Hwang, W: AUTHOR [+2]

Abstract

Disclosed is a self-synchronizer circuit to solve the mismatching problem of the incoming pulses for self-resetting complementary metal oxide semiconductor (CMOS) circuits [1]. The circuit consists of two function blocks as shown Fig. 1. The first function block (indicated as I) is the self-timed elements which uses to synchronize the incoming pulses regardless of their relative arriving time. The second function block (indicated as II) is the latches which holds incoming signals temporarily and then generates pulses simultaneously when the last signal is arrived. The block I has four input terminals (A, B, C, and D) and one output terminal (Y). The block II has five input terminals (A, B, C, D, and INT) and three output terminals (X, Y, and Z).

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Self-Synchronizer for Self-Resetting Complementary Metal Oxide Semiconductor Circuits

      Disclosed is a self-synchronizer  circuit  to  solve  the
mismatching   problem   of   the   incoming    pulses    for
self-resetting  complementary metal oxide semiconductor (CMOS)
circuits  [1].  The circuit consists of two function blocks as shown
Fig.  1.  The  first  function block (indicated as I) is the
self-timed elements which uses to  synchronize  the  incoming  pulses
regardless  of their relative arriving time.  The second function
block (indicated as  II)  is  the  latches  which  holds   incoming
signals temporarily  and  then  generates pulses simultaneously when
the last signal is arrived.  The  block  I  has  four  input
terminals  (A, B, C, and D) and one output terminal (Y).  The block
II has five input terminals (A, B, C, D, and INT)  and three output
terminals (X, Y, and Z).  The new four dual-rail input-signal
self-synchronizer is connected as shown in Fig.  1.    The  A1,A2,
B1,B2,  C1,C2,  and  D1,D2  are  the four dual-rail signals of the
input logic  pulse  terminals.  The incoming  asynchronous  pulses
are  received  through these terminals.  The INT input is the
initialization terminal for the cold start to initialize all the
block I elements to low state.  The S1,S2, X1,X2, Y1,Y2, and Z1,Z2
are four dual-rail output terminals.  The outgoing synchronous pulses
are  sent out through these terminals.

      The  disclosed  latches which holds each incoming logic signals
temporarily is shown in Fig 2.   A1 and A2  are  the dual-rail
signals  of  the input logic pulse.  A1 and A2 are connected to input
terminal A and B,  respectively.  The  OR circuit will detect the
incoming pulse from either rail.  INT input  is  the initialization
terminal for the cold start to initialize all the Muller C-elements

[2]  to low state which turns device 12 on and reset latch 23 into
low state.  BA and BB  are the input terminals for the Muller-C
result.  BA and BB  are  also  connected  to  input  terminal   C
and   D, respectively.  Section 11 is the delay line which is used to
adjust the pulse width.

      At  the  cold...