Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Method to Display Timing Results during Floorplanning

IP.com Disclosure Number: IPCOM000104340D
Original Publication Date: 1993-Apr-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 115K

Publishing Venue

IBM

Related People

Huber, G: AUTHOR [+4]

Abstract

Disclosed is a method to display the results of timing analysis of a chip in conjunction with the display of a physical view of a floorplan of the chip. The purpose of the timing display is to show graphically the effect on chip timing caused by changes in the chip floorplan. It also helps the designer understand a timing path in the chip with respect to the floorplan of the chip.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 47% of the total text.

Method to Display Timing Results during Floorplanning

      Disclosed  is  a  method  to  display  the results of timing
analysis of a chip in conjunction  with  the  display  of  a physical
view  of  a floorplan of the chip.  The purpose of the timing display
is to show graphically the effect on chip timing caused by changes in
the  chip  floorplan.  It  also helps the designer understand a
timing path in the chip with respect to the floorplan of the chip.

      Timing  analysis  and verification is an important step in the
design process for high performance computers.    The timing   of
signals  in  a  design  are  usually  specified explicitly at certain
points called test points.  Usual  test points  in  computer  designs
are latches.  In order for the computer to function properly, the
signals  must  arrive  at the  test  points within a specified time.
Paths of interest to timing analysis typically end at these test
points.   The objectives considered during timing analysis are as
follows:

o   Verify  that a given machine design meets its cycle time goals.

o   Detect timing problems such as late and early paths.
o   For  each  path,  compute  the  difference  between  the desired
    and  the  actual  timing  results, often called slack.
o   Provide feedback to the designer as  to  the  effect  of changes
    in  the design on the timing characteristics of the machine.

      Conventional  timing  analysis  programs   return   the results
in  the  form of extensive slack lists.  These slack lists usually
enumerate all the paths in  the  design  which have  slacks  below  a
certain user defined threshold.  Each path consists of a sequence of
segments, where each  segment represents  two points between which
the signal must travel.  The arrival times, required arrival times
and the  slack  of the  signal at each of these segments is usually
produced as outputs of timing analysis.  These slack lists  are
usually written  out  to a file at the end of timing analysis.  This
conventional method of reporting timing analysis results  is not
suitable for use in floorplanning.  During floorplanning, the
designer needs to understand the effect of any floorplan change  on
the  timing  of  the  system.  Furthermore,  the designer needs to
understand each timing path in relation to floorplan  macros.  Also,
it is not possible to enumerate the timing paths in detail; a
condensed display is desirable.

      A flow chart of the method is  shown  in  Fig. 1.  The various
steps in the method and the different components of the interface are
described below.

      Timing  analysis  is   performed   using   well   known
algorithms.  This  step  is  required  before results can be
displayed.  The cycle time for the entire design, as well  as the
cycle  time  for  the  chip  under consideration in...