Browse Prior Art Database

Floating Point Store Remapping

IP.com Disclosure Number: IPCOM000104346D
Original Publication Date: 1993-Apr-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Chu, TV: AUTHOR [+3]

Abstract

Disclosed is a method for obtaining the benefits of a fixed field instruction architecture in the POWER* and PowerPC architectures*. The advantages of a fixed field instruction architecture can be gained in an architecture which does not have fixed fields on every instruction by moving the non-fixed fields into the appropriate fields at dispatch time, instead of at execution time.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 72% of the total text.

Floating Point Store Remapping

      Disclosed is a method for obtaining the benefits of a fixed
field instruction architecture in the POWER* and PowerPC
architectures*.  The advantages of a fixed field instruction
architecture can be gained in an architecture which does not have
fixed fields on every instruction by moving the non-fixed fields into
the appropriate fields at dispatch time, instead of at execution
time.

      A fixed field instruction architecture is one in which source
and target register addresses are contained in the same bit lanes for
every instruction.  This allows execution units to directly access
GPRs (general purpose registers) without having to first find the GPR
addresses.

      The RS/6000* floating point architecture has a fixed field
instruction architecture except for floating point stores.  Floating
point stores have the source register in what is normally the target
register location.  The reason for this is that the bit lanes
normally used by source operands are used for the EA (effective
address) generation register addresses or the displacement field in
the case of D-form addressing.  Thus, in order to have a fixed field
format for the EA generation unit, the store instructions must use
what is generally a target register address field as the source
register address field.

      For implementations in which the GPR access is later than
dispatch time, the floating point source register address field can
be copied ont...