Browse Prior Art Database

Design Approach to Relief Chip I/O Constraint

IP.com Disclosure Number: IPCOM000104365D
Original Publication Date: 1993-Apr-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 132K

Publishing Venue

IBM

Related People

J Chang, H: AUTHOR [+4]

Abstract

Disclosed are design techniques to significantly relief the pin-in and pin-out limitations of chips.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 50% of the total text.

Design Approach to Relief Chip I/O Constraint

      Disclosed  are design techniques to significantly relief the
pin-in and pin-out limitations of chips.

      Modern  processor/computer  design  faces  many  critical
technology  constraints.   One of them is the number of chip i/o's
(input and output pins).  Since it is a  very  limited resource, how
to deploy them efficiently become increasingly important and critical
to the design of the system.

      In  general,  data communicated between chips are through
DEDICATED bus and chip i/o's even in  the  case  where  many buses
from different chips are going into the same receiving chip  or  in
the case where many buses transmitted from the same chip into
different chips.

      However, a bus may be active in only certain cycle(s)  of the
machine  in  many  cases.  If we know one incoming data group (bus)
is active in certain  cycle(s)  and  other  data group  is active in
other mutually exclusive cycle(s) of the system, a bus (chip i/o's)
sharing mechanism can be  devised to save the chip i/o's of the
receiving chip and thus gives relief to the design.

      The  invention  presents a bus (chip i/o's) sharing mechanism
and its control techniques.  This allows us to use the same i/o pins
of a chip for receiving/transmitting different data groups from/into
other different chip(s),  as  long  as these  data  groups  are not
active in the same cycle of the machine.  The basic idea is to use a
register,  called  the cycle-time register, to point to a cycle-time
number associated  with  the current cycle of the machine (e.g., k
for the cycle C(k)), where a reference cycle-time information should
be generated and used to reset the  cycle-time  register to the
reference  cycle-time  number  (e.g. 0 for C(0) cycle).  The current
cycle-time number will be used to control a selector  for routing the
incoming data into one desired functional  block  in  the  chip  or
ungating  (selecting)  the incoming  data  group for using in the
right cycle time.  In non-active cycles of data groups, their
communication  lines should  be  forced to all o's as most common
practices; then we can perform wiring-OR of all  data  lines  and
multiplex them into the same i/o pins without interference.

      Illustrated is an example of receiving different data group
through the same input pins of the chip (Fig. 1(a)).  Assume each
chip of the chips A, B, C, D, and E needs to send a K-bit data group
(including a valid bit) to the chip F, and all these 5 K-bit data
groups are not active at the same time.  For simple illustration,
also assume the data groups from the chips A and B are active in only
C(0) cycle, the data group from the chip C is active in only C(1)
cycle, the data group from the chip D is active in only C(2) cycle,
and the data group from the chip E is active  in  only  C(3) cycle.
In  normal practice, each K-...