Browse Prior Art Database

Enhanced Solder Bump Retention on Solder Decals

IP.com Disclosure Number: IPCOM000104366D
Original Publication Date: 1993-Apr-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 83K

Publishing Venue

IBM

Related People

Hayden, TF: AUTHOR [+3]

Abstract

Disclosed are two processing techniques which enhance the yield of solder decals for direct chip attachment.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Enhanced Solder Bump Retention on Solder Decals

      Disclosed are two processing techniques which enhance the yield
of solder decals for direct chip attachment.

      Solder decals are used for applying controlled amounts of
(typically eutectic) tin/lead solder to sites on circuit carriers to
allow the attachment of C4 chips.  In the typical process for
producing solder decals, photoresist is applied to a stainless steel
substrate, imaged and developed to produce a pattern of holes which
correspond to the chip C4 footprint.  Tin/lead solder is then
electroplated into these cavities and the photoresist removed.  The
pattern of solder deposits on the stainless steel substrate (termed a
"solder decal") can then be thermally transferred to the circuit
carrier.  During the transfer process, solder dewets from the
stainless steel substrate and wets (typically) copper pads or lines
on the circuit carrier.

      This disclosure describes two processing techniques which have
been shown to greatly enhance the yield of good decals, that is,
decals with all solder bumps present and of uniform volume.

      The first technique involves imparting a very fine surface
roughness to areas of the metal panel (containing precut decal parts)
which will be plated with solder.  This can be accomplished by either
mechanical or chemical means.  Mechanically, a grit-blasting
technique using 25 to 50&mu.  aluminum oxide powder applied at a
pressure of 100 psi has been quite effective at producing a surface
finish of 300 nm Ra to 600 nm Ra.  This surface finish increases the
surface area available for plating while not introducing warpage to
the metal part.  By increasing the effective surface area in contact
between bump and substrate, adherence of solder bumps to the
substrate is enhanced.  More severe mechanical surface treatments can
introduce compressive stresses into the metal surface causing a
warping or nonplanarity of the decal.  The nonplanarity leads to
nonuniform contact of solder bumps to the mating sites of the circuit
carrier during reflow.

      Chemical treatments, such as those listed below...