Browse Prior Art Database

Input Separation Based on Sub-Cones for Delay Test

IP.com Disclosure Number: IPCOM000104373D
Original Publication Date: 1993-Apr-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 105K

Publishing Venue

IBM

Related People

Patil, S: AUTHOR [+2]

Abstract

Disclosed is a procedure to increase the delay fault coverage for combinational logic circuits by using a technique called input separation based on sub-cones.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Input Separation Based on Sub-Cones for Delay Test

      Disclosed is a procedure to increase the delay fault coverage
for combinational logic circuits by using a technique called input
separation based on sub-cones.

      The proposed method provides an alternative to the method
presented in [1]  in cases where one is not allowed to use dummy
latches.  The proposed method is based on fault simulation of the
logic circuits which allows one to concentrate on only those portions
of the circuit where undetectable transition faults exist.

      Before discussing the actual algorithm, the method using a
simple example will be illustrated.  Consider the circuit shown in
Fig. 1 which is a cascade of three AND gates.  This example can be
shown to belong to a family of worst-case examples for transition
fault coverages using skewed load.  Now consider the scan path
ordering of inputs to be 1 >  2 >  3 >  4.  Denote a slow-to-rise
fault by  A and a slow-to-fall fault by V.  This is actually the
worst possible ordering for this circuit and 5 of the 14 faults turn
out to be undetectable (1 A, 2 A, 3 A, 5 A  and 6 A) giving a fault
coverage figure of 64%.  If inputs are considered to be at level 1,
there are 3 undetectable faults at level 1, 1 at level 2 and 1 at
level 3.  A plot of undetectable faults versus logic are shown in
Fig. 2.  This will be called the undetectability profile.  Since all
5 undetectable faults of interest occur at level 3 or lower, we are
going to 'splice' the circuit at level 3 as shown by the vertical
line in Fig. 1.  Secondary outputs were then created wherever the
imaginary line cuts - in the case of our example, at lines 4 and 6.
For the purpose of re-ordering, it was assumed that there are outputs
at lines 4 and 6.  Thus, inputs 1, 2 and 3 depend on output 6, input
4 depends on output 4.  Using the greedy method given in [1], and
without using any dummy latches, the result is the scan path ordering
1 >  4 >  2 >  3 which gives a coverage 79%.  This figure is also the
maximum possible coverage for the example circuit without the use of
dummy latches.  Since this algorithm is heuristic in nature, it is
not always guaranteed to find the optimal ordering.

The actual algorithm is outlined below:

1.  First, levelize or rank-order the circuit.  Set the iteration
    count iter to 1.  Assume the maximum allowable iterations are
    given by iter sub 'max'.

2.  Perform transition fault simulation on the circuit using an
    efficient fault simulation algorithm like PPSFP [2] and assuming
    some random ordering of inputs in the scan chain and skewed load
    of vector pairs.

3.  Plot the undetectability profile (similar to the plot shown in
    Fig. 2).

4.  Let L sub 'max' be the maximum number of logic levels in the
...