Browse Prior Art Database

Convert to Binary Execution Reduced to 3 Cycles

IP.com Disclosure Number: IPCOM000104384D
Original Publication Date: 1993-Apr-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Maass, KK: AUTHOR

Abstract

Disclosed is a system that allows the conversion from decimal to binary in 3 cycles when using the logic blocks depicted in the figure and the fact that only 10 digits can be converted and be contained in a 32 bit word.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 84% of the total text.

Convert to Binary Execution Reduced to 3 Cycles

      Disclosed is a system that allows the conversion from decimal
to binary in 3 cycles when using the logic blocks depicted in the
figure and the fact that only 10 digits can be converted and be
contained in a 32 bit word.

      To be more specific, that maximum decimal that can be converted
and contained in a 32 bit word is 214 7483647

                 Decimal Number
HIWD   0 0 0 0 0 2 1 4      7 4 8 3 6 4 7 S    LOWD

       0 0 0 0 0 Ao Bo Co   Do A1 B1 C1 D1 A2 B2 S

When 0-21 of the HIWD of the decimal number is detected to be zero,
the CVB instruction can be executed in 3 cycles.  When 0-21 of the
HIWD of the decimal number is detected to be not zero, the CVB
instruction will signal an exception and will execute in either 4 or
5 cycle depending on the sign of the converted number.

The 3 cycle execution converts in cycle 4 HIWD AoBoCo LOWD Do
                                  cycle 1 LOWD A1B1C1D1
                                  cycle 0 LOWD A2B2
Followed by a 2 complement if the result is to be neg.

      The 3 cycle execution is made possible because 10 digits needed
conversion and no more.  This allows the second CPA (CPA2) in the
figure to be used as a complementer in cycle 0, when the result must
be made negative.

If HIWD bits 0 - 21 = 0    (Fixpoint divide exception)

HIWD   Ao Bo Co Do A1 B1 C1...