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Corrosion and Electromigration-Resistant High-Conductivity VLSI Interconnects

IP.com Disclosure Number: IPCOM000104408D
Original Publication Date: 1993-Apr-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 160K

Publishing Venue

IBM

Related People

Aboelfotoh, MO: AUTHOR [+2]

Abstract

A metallurgy is described for VLSI interconnects which achieves the highest possible conductivity while simultaneously possessing immunity to corrosion and electromigration damage. These interconnects can be made at low temperatures but are stable to much higher temperatures, consistent with modern processing technologies.

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Corrosion and Electromigration-Resistant High-Conductivity VLSI Interconnects

      A metallurgy is described for VLSI interconnects which achieves
the highest possible conductivity while simultaneously possessing
immunity to corrosion and electromigration damage.  These
interconnects can be made at low temperatures but are stable to much
higher temperatures, consistent with modern processing technologies.

In addition, the process is self-aligned and amenable to submicron
design dimensions.

     The metallurgy consists of pure copper interconnections which
are fully encapsulated with reactively formed Cu&sub3.Ge (copper
germanide).  Thin films of Cu&sub3.Ge have a resistivity of 5.5
&mu.&Omega.-cm [1] which is lower than most metals and alloys.  It is
chemically very inert, and does not oxidize.  It does not exhibit
electromigration, and yet is still ductile, but has a hardness
similar to nickel.  It is formed easily at temperatures as low as 150
ºC when copper and germanium are in contact, so long as silicon
is not also in contact, and is stable to above 600 ºC [1].  Two
processes are described below as possible implementations: first, for
the case of patterned dielectric which is subsequently filled with
the interconnect; second for patterned interconnects which are
subsequently filled with the dielectric insulator.

     In Fig.1 (a) the polyimide has been applied, cured, and
patterned to accomodate lines or studs.  A thin (~300 A),
conformal film of pure germanium is then applied by CVD or sputtering
(b), then 450 A pure copper is applied by either sputtering, CVD, or
plating, such that the patterns are completely filled (c).  Next, a
low-temperature anneal completes the Cu&sub3.Ge reaction.  The sample
is polished by CMP to expose the tops of the copper lines (d).  The
intra-wire Cu&sub3.Ge is removed by selective etch (e).  A blanket
film of Ge is then applied, and annealed to react with the copper
line tops (f).  At this point the lines are fully encapsulated, and
the Ge may be removed by a selective wet chemical etch (g).

     In Fig.2, the metal is deposited first over a thin film of
germanium  (a), (b) an...