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Modified L2 Cache Replacement for Retaining Hot L1 Cache Lines

IP.com Disclosure Number: IPCOM000104424D
Original Publication Date: 1993-Apr-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Kirkpatrick, S: AUTHOR [+3]

Abstract

Disclosed is a shared memory multiprocessor (MP) system in which each processor (CPU) accesses the memory through a hierarchy of storage: Level-one cache (L1), Level-two cache (L2) and the shared memory. Each CPU has its own L1 and L2 caches (possibly more than one L1 cache shares an L2 cache), and all the L2 caches communicate with each other through a system bus or a control unit. In such a system, because a piece of data can reside in multiple caches at the same time, some amount of cross interrogations (XIs) from one L2 cache to its remote L1 or L2 caches are needed to maintain the coherence of data sharing among the CPUs. The effectiveness of a cache, especially at an L1 cache, can be drastically reduced if it is contented by the accesses from its local CPU and the XIs from remote CPUs.

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Modified L2 Cache Replacement for Retaining Hot L1 Cache Lines

      Disclosed is a shared memory multiprocessor (MP) system in
which each processor (CPU) accesses the memory through a hierarchy of
storage: Level-one cache (L1), Level-two cache (L2) and the shared
memory.  Each CPU has its own L1 and L2 caches (possibly more than
one L1 cache shares an L2 cache), and all the L2 caches communicate
with each other through a system bus or a control unit.  In such a
system, because a piece of data can reside in multiple caches at the
same time, some amount of cross interrogations (XIs) from one L2
cache to its remote L1 or L2 caches are needed to maintain the
coherence of data sharing among the CPUs.  The effectiveness of a
cache, especially at an L1 cache, can be drastically reduced if it is
contented by the accesses from its local CPU and the XIs from remote
CPUs.

     One approach for reducing the amount of XIs at the L1 caches is
to enforce an inclusion property between the L1 and L2 caches in a
way that the content of the L1 cache is always a subset of its L2
cache and it is possible to tell from the L2 if a line is currently
residing in its L1 or not.  In this case, an L1 cache is interfered
if it really contains a line being accessed by a remote CPU.  This
inclusion property requires that whenever an L2 line is to be
replaced, any parts of it currently residing in its L1 cache(s)
needed to be replaced from L1 also.  However, because the replacement
status of L2 cache lines is determined by the L1 cache miss sequence
but not the CPUs memory reference sequence as for the L1 cache lines,
an L2 line which contains frequently accessed (hot) L1 lines is
rarely accessed and is likely to be replaced from L2 under the
least-recent...