Browse Prior Art Database

Hardware Removal of Dependencies from Sequentially Queued Operations

IP.com Disclosure Number: IPCOM000104426D
Original Publication Date: 1993-Apr-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Carnevale, MJ: AUTHOR [+3]

Abstract

Disclosed is a method for removing dependencies from sequentially queued operations. When operations are stacked in a queue, subsequent operations must be careful not to alter control fields (registers, mode bits, etc.) that provide information as to the state of the system at the time the queued operations were dispatched.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 62% of the total text.

Hardware Removal of Dependencies from Sequentially Queued Operations

      Disclosed is a method for removing dependencies from
sequentially queued operations.  When operations are stacked in a
queue, subsequent operations must be careful not to alter control
fields (registers, mode bits, etc.)  that provide information as to
the state of the system at the time the queued operations were
dispatched.

      This method will cause an operation to 'carry' with it all the
control information it is dependent on at the time it was dispatched
to the queue.

      Fig. 1 shows a simplified drawing of an instruction dispatching
unit, a general purpose register stack, and two parallel execution
units.  The storage (memory) execution unit in this example contains
a queue because memory is often busy due to access times, refreshing,
and often being a shared system resource (as in the multi-processing
environment or in an I/O environment due to DMAs by an IOA).  In the
example, instruction A and D are executing concurrently.  The next
instruction to be dispatched, instruction E, will use the execution
unit to ADD registers 2 and 3 together with the result being stored
to register 3.  Normally, instruction E can be dispatched right away
but, because queued storage instruction C will use register 3 to
generate a storage address, instruction E will have to wait until
instruction C gets to the bottom of the storage queue and actually
begins executing.  This slows overall ...