Browse Prior Art Database

Buffer Notification Mechanism for Personal Computers

IP.com Disclosure Number: IPCOM000104432D
Original Publication Date: 1993-Apr-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 75K

Publishing Venue

IBM

Related People

Claffey-Cohen, ME: AUTHOR [+4]

Abstract

Described is a buffer notification mechanism for personal computers (PCs) equipped with an internal buffering parallel port, as used in continuous high speed protocol operations. The mechanism disables an asynchronous interface and notifies of an empty condition through the use of a control bit.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 73% of the total text.

Buffer Notification Mechanism for Personal Computers

      Described is a buffer notification mechanism for personal
computers (PCs) equipped with an internal buffering parallel port, as
used in continuous high speed protocol operations.  The mechanism
disables an asynchronous interface and notifies of an empty condition
through the use of a control bit.

      In prior art, an internal first-in-first-out (FIFO) buffering
mechanism was added to the PC parallel port in order to accommodate
the continuous data rate requirement of the high speed parallel port
protocol.  The concept described herein enhances the prior art
mechanism by enabling software to programmably empty the FIFO when
receiving data from a parallel port connected device.  The mechanism
synchronously disables the parallel port interface to ensure that no
further data is received from the remote device.  In addition, the
mechanism ensures that any remaining data in the FIFO is sent to the
system and that a notification is made available.

      The mechanism uses the programmable empty-FIFO bit in the 64
byte bus master stack register at the address 15H.  Fig. 1 shows the
stack with the address 15H designation.  Address 15H will be first
powered low, logic '0'.  When the empty-FIFO bit is written high,
logic '1', the FIFO will signal to the receive high speed parallel
port protocol that the system is not ready, or is in a busy state, so
that the FIFO stops to receive data from the remote dev...