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Browse Prior Art Database

Self-Aligned Contact Technology

IP.com Disclosure Number: IPCOM000104446D
Original Publication Date: 1993-Apr-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 68K

Publishing Venue

IBM

Related People

Ng, H: AUTHOR [+4]

Abstract

A process technology has been developed that produces self-aligned diffusion and gate electrode contacts for technologies with minimum dimensions of less than 0.3um.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 63% of the total text.

Self-Aligned Contact Technology

      A  process  technology has been developed that produces
self-aligned diffusion and gate electrode  contacts for technologies
with minimum dimensions of less than 0.3um.

      The disclosed process is as follows: The gate electrode films
are deposited and may be a composite of several films, such as
polysilicon and titanium silicide.  Boron nitride (BN) is deposited
as the gate electrode cap and is deposited to a thickness equal to
the desired gate contact stud height.  The gate  electrode  resist
is  patterned and the gate stack is etched.  The resist  is  stripped
and  the  wafers  cleaned.  Silicon nitride is deposited and reactive
ion etching (RIE) etched to form nitride spacers.  Now the silicided
junctions  are  formed.  The resulting structure to this point in the
process is shown in step A.  A  short  diluted hydrogen fluoride (HF)
clean is done, followed by tungsten silicide (WSi sub 2) deposition
and RIE etched to form tungsten silicide sidewall spacers, as shown
in step B.  Lateral  width  of  the  spacers  is chosen according to
the desired diffusion contact dimension.  Deposit chemical vacuum
deposition (CVD) oxide  and planarize to the top of the gate stack.
Define the blockout photo level so that resist  will  cover  WSi sub
2 sidewall spacers  that  will  be  used  as  diffusion  contact
studs.  Tungsten silicide spacers that are not  used  for  diffusion
contact  stud...