Browse Prior Art Database

Non-Processor Based Zero Waitstate MICRO CHANNEL Bus Master State Machine

IP.com Disclosure Number: IPCOM000104467D
Original Publication Date: 1993-Apr-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 64K

Publishing Venue

IBM

Related People

Ward, JP: AUTHOR

Abstract

Described is an architectural implementation to provide a non-processor based state machine that supports zero waitstate MICRO CHANNEL* (MC) bus cycles, as used in personal computer systems.

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This is the abbreviated version, containing approximately 66% of the total text.

Non-Processor Based Zero Waitstate MICRO CHANNEL Bus Master State Machine

      Described is an architectural implementation to provide a
non-processor based state machine that supports zero waitstate MICRO
CHANNEL* (MC) bus cycles, as used in personal computer systems.

      Typically, a MC device that operates as a busmaster has the
ability to generate and interpret timing signals.  The timing
relationships of the timing signals are critical and requires a high
degree of precision in the logic design to assure that all of the
timings are satisfied.  This is particularly important in zero
waitstate MC cycle configurations.  In prior art, microprocessors
were incorporated as a busmaster interface in the MC design to
provide the zero waitstate function.  This increased the cost and
reduced the performance of the system.

      The described concept provides a means of providing zero
waitstate MC bus master functions without the need of a
microprocessor.  Fig. 1 shows an architectural logic block diagram of
the busmaster state machine.  The seven functional states are shown
for this implementation.  Figs. 2, 3 and 4 show the timing charts
associated with the state machine logic at the various cycle phases:
default cycle, sync ext cycle, and async ext cycle, respectively.
Each state corresponds to one clock period with all state transitions
taking place on the rising edge of the clock signal.

      Critical to the success of this design flow is the min...