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Interleaving through Frame Buffers

IP.com Disclosure Number: IPCOM000104476D
Original Publication Date: 1993-Apr-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 85K

Publishing Venue

IBM

Related People

Lawless, W: AUTHOR

Abstract

In today's graphics designs, performance is of most importance. As seen through many studies there are several bottlenecks when rendering pixels into frame buffers that hinder performance. One is the bandwidth of the pixel bus into the frame buffers themselves. As the density of video memory became greater it took fewer and fewer memory chips for frame buffer storage. This was a big advantage for card real estate and number of pins on cards and cost. However, when communicating with fewer memory chips the bus bandwidth went down causing a problem in performance. The following article will show how to use the same actual number of memory chips and increase Bus Bandwidth to increase performance.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Interleaving through Frame Buffers

      In today's graphics designs, performance is of most importance.
As seen through many studies there are several bottlenecks when
rendering pixels into frame buffers that hinder performance.  One is
the bandwidth of the pixel bus into the frame buffers themselves.  As
the density of video memory became greater it took fewer and fewer
memory chips for frame buffer storage.  This was a big advantage for
card real estate and number of pins on cards and cost.  However, when
communicating with fewer memory chips the bus bandwidth went down
causing a problem in performance.  The following article will show
how to use the same actual number of memory chips and increase Bus
Bandwidth to increase performance.

      This article will talk about a graphics design using 16 bits
per pixel.  One frame buffer of 8 bits and 8 bits of window
IDs/overlays.  However, this will work with two frame buffers and
window planes as well with additional increase in bus bandwidth and
even better performance.

      Frame Buffers should be organized as shown in Fig. 1.  For ease
of drawing 2 meg VRAM chips (512 x 512 x 8) are used to create a 1280
x 1024 screen size.

      Screen bits should be organized as shown in Fig. 2.

      The inventive idea here is when writing a group of horizontal
pixels you can write 10 pixels instead of 5.  But most importantly
when scanning out the data to the RAMDAC for display the WID buffers
are scanned out to the screen at the same time.  For example, when
writing 10 pixels into frame buffer 0, addressing would be like this:

R = Row Address, C = Column Address, # = Module...