Browse Prior Art Database

Sige Interface Reduction Approach

IP.com Disclosure Number: IPCOM000104482D
Original Publication Date: 1993-Apr-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 95K

Publishing Venue

IBM

Related People

Comfort, JH: AUTHOR [+6]

Abstract

In complex BiCMOS processes poly-poly interfaces often occur as a result of trying to share poly layers to reduce process complexity. The presence of an oxide at the poly-poly interface can cause dopant distribution/activation and etch/bias problems where it occurs in MOS gates, bipolar extrinsic base, and bipolar emitter polysilicon layers. By finishing up a previous layer with SiGe and/or starting the second decomposition with SiGe the oxide content can be drastically reduced.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Sige Interface Reduction Approach

      In complex BiCMOS processes poly-poly interfaces often occur as
a result of trying to share poly layers to reduce process complexity.
The  presence  of  an  oxide at the poly-poly interface  can  cause
dopant  distribution/activation   and etch/bias  problems  where  it
occurs in MOS gates, bipolar extrinsic base, and bipolar emitter
polysilicon layers.   By finishing  up a previous layer with SiGe
and/or starting the second decomposition with SiGe  the  oxide
content  can  be drastically reduced.

      The  invention  will be demonstrated by pointing out its use in
a BiCMOS process with  a  double  poly-self  aligned  NPN transistor.
In certain embodiments a polysilicon layer can be used for both the
extrinsic base of the bipolar  and  MOS gate polysilicon stack.  In
this approach, it is advantageous to  form  the  MOS gate oxide prior
to this shared base-gate polysilicon deposition and to protect the
gate  oxide  from processing  conditions  by  depositing  a  thin
polysilicon layer.  This layer is called a poly-protect layer since
its main purpose is  to protect the gate oxide.   This is shown in
Fig. 1.  The poly protect layer and gate oxide is then removed over
the NPN bipolar area by means of a masking and  etching  step.  The
extrinsic  base  polysilicon  is deposited  over  the  NPN  area
with  conventional  LPCVD technology.   This leaves an  oxide
interface  between  the extrinsic  base  and  poly-protect
polysilicon layers.   The structure at this  point  is  shown  in
Fig. 2.    If  a d...