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Browse Prior Art Database

Condition Register Coherency Look-Ahead

IP.com Disclosure Number: IPCOM000104505D
Original Publication Date: 1993-Apr-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 1 page(s) / 32K

Publishing Venue

IBM

Related People

Muhich, JS: AUTHOR [+2]

Abstract

Disclosed is a method for determining the coherency of the condition register (CR) in a pipelined processor, thus allowing conditional branches higher in the pipeline to be resolved as early as possible.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Condition Register Coherency Look-Ahead

      Disclosed is a method for determining the coherency of the
condition register (CR) in a pipelined processor, thus allowing
conditional branches higher in the pipeline to be resolved as early
as possible.

      In pipelined processors, performance is heavily dependent on
branch delays caused by redirecting the instruction stream and
subsequently refilling the pipeline.  The higher in the pipeline that
a redirection is detected, the smaller the branch delay.

      It is possible to determine the coherency of the CR on a field
by field basis quickly by generating a tag for each instruction which
describes the CR fields being updated by that instruction.  When the
update occurs, the tag can be either ignored or removed.  When a
conditional branch occurance is detected, the CR coherency tags lower
in the pipeline are checked - if no instructions are updating the CR,
then the branch can safely be resolved based on the current CR.  If
instructions are updating the CR then the branch must wait for those
instructions to complete.

      If register renaming on the CR is supported, then this tag
system can be used to find the most recent CR value even if the
architected CR update has not yet occurred.

      This 'early CR checking' can significantly reduce the
mistopdict penalty for conditional branches.

Disclosed Anonymously.