Browse Prior Art Database

Single Cache for Instruction and Exec Units Parallel Access and Partitioning

IP.com Disclosure Number: IPCOM000104506D
Original Publication Date: 1993-Apr-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 1 page(s) / 49K

Publishing Venue

IBM

Related People

Howell, LC: AUTHOR

Abstract

Disclosed is a single cache unit which allows access by an instruction unit and a execution unit within a cycle while still allowing separate cache partitions.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 56% of the total text.

Single Cache for Instruction and Exec Units Parallel Access and Partitioning

      Disclosed is a single cache unit which allows access by an
instruction unit and a execution unit within a cycle while still
allowing separate cache partitions.

      There are 2 approaches to cache computer architecture.  The
first approach is a cache feeding the instruction unit and another
cache for the execution unit.  The second is to have both of these
units using the same cache and sharing the same addresses.  The
separate caches function more efficiently than the combined cache
since parallel operations can be performed and each of their sizes
can be optimized.  However, the separate caches also have the expense
of duplicate functions (memory request processing, built-in testing
logic, physical redundant row burn in, cache chip placement, and
wiring).  The following design has the advantages of both approaches.

      By using a pipeline cache with 2 ports, a read/write can be
performed by a unit in the first half cycle and another read/write
performed by the other unit in the second half.  The order of
operation could be fixed for port 0 to always go first.  Or the port
order could be altered with a simple master/slave relationship
between the units where a signal is sent to the cache indicating
which port should go first.  The determination of which unit should
go first is dependent on who needs the data more urgently.

      The following procedure explains...