Browse Prior Art Database

Representation of Physical Placements in a Schematic Logical Design

IP.com Disclosure Number: IPCOM000104514D
Original Publication Date: 1993-Apr-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 1 page(s) / 31K

Publishing Venue

IBM

Related People

Whitley, WP: AUTHOR

Abstract

Disclosed is a method for representing a logical design in schematic form, using the physical schematic placement of components and wires, thereby combining the logical and physical representations of the design.

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This is the abbreviated version, containing approximately 100% of the total text.

Representation of Physical Placements in a Schematic Logical Design

      Disclosed is a method for representing a logical design in
schematic form, using the physical schematic placement of components
and wires, thereby combining the logical and physical representations
of the design.

      The physical representation of a logical component, such as a
circuit module, typically provides a functional grouping of various
signal lines for physical layout and routing.  This grouping is
maintained, and logical schematics are developed to provide an
improved representation of the design in schematic form, by using a
process begun by designing component models which are representative
of the actual shape and footprint of each part.  Such models include
physical pin numbers in the correct sequence.  These component models
are then placed according to functional groupings on each schematic
page, with major components being placed first and peripherals being
placed second.  Components are then oriented, by rotation and
alignment, to minimize interconnection distances and crossings.
Critical clocks are connected first, with busses being connected
next, and with control lines being connected last.  Finally,
decoupling capacitors are added, and the schematics are cleaned up.

Disclosed Anonymously.