Browse Prior Art Database

Redundant Oscillator Method

IP.com Disclosure Number: IPCOM000104577D
Original Publication Date: 1993-May-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Gillingham, RD: AUTHOR [+2]

Abstract

In a computer system, the clocking is derived from a crystal oscillator. To improve system reliability, it is advantageous to automatically switch from a failing crystal oscillator to a second oscillator without the failure being detected. The method described allows such operation.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 66% of the total text.

Redundant Oscillator Method

      In a computer system, the clocking is derived from a crystal
oscillator.  To improve system reliability, it is advantageous to
automatically switch from a failing crystal oscillator to a second
oscillator without the failure being detected.  The method described
allows such operation.

      The circuit is presented in the figure.  The object of the
circuit is to provide multiple copies of a clock signal 7 to computer
logic circuits.

      The two oscillators, OSC1, OSC2, enter a mux 5, and one is
selected to pass to the PLL 6.  The decision as to which oscillator
signal to pass is made by the oscillator fail detect circuits 1 and
2, the power-on reset 3, and the latch 4.  The decision appears
logically at the mux control line 8.

      The oscillator detect circuits 1 and 2 can be any circuit which
senses a faulty oscillator.  These circuits should detect the error
quickly to keep the PLL input from deviating from the design
frequency.

      The power-on reset 3 sets the latch to a known state at
power-on.  For the figure shown, the latch is reset at power-on and
oscillator 1 is selected by the mux.  Oscillator 1 will continue to
be selected at the end of the power-on reset until oscillator 1
fails.  At that time, the oscillator fail detect 1 will switch,
causing the latch 4 to become active.  The latch output will switch,
causing the mux 5 to select oscillator 2 (OSC2).  Oscillator 2 will
then remain selec...