T3 Delay Simulator
Original Publication Date: 1993-May-01
Included in the Prior Art Database: 2005-Mar-19
Disclosed is a test tool to simulate city-to-city, cross-country propagation delays of common carrier T3, or satellite links.
T3 Delay Simulator
a test tool to simulate city-to-city,
cross-country propagation delays of common carrier T3, or satellite
uses an IBM 3172 Interconnect Controller Model 2
platform and HSSI (high speed serial interface) or T3 adapters.
1.2 and 1.3 illustrate a T3 link, a satellite link
and the use of a T3 Delay Simulator.
simulates the delay caused by the transmission of
signals over large distances. For example, assuming 4.92
microseconds/km for long haul fiber (about 0.70 times the speed of
light in free space), the following one-way propagation delays are
mi) 24.0 milliseconds
3220.6 km(2000 mi) 16.0 milliseconds
1610.3 km(1000 mi) 8.0 milliseconds
satellite link transmission, the following
approximate one-way figures are assumed.
Local earth station to Satellite 1 135.0 milliseconds
Satellite 1 to
Satellite 2 100.0
Satellite 2 to remote earth station 135.0 milliseconds
Total (to nearest hundred) 400.0 milliseconds
delays through the simulator are dependent upon actual
packet lengths and their incoming arrival rates as well as other
factors. The simulator is not able to produce a delay smaller than
the minimum delay a packet must incur in being processed through the
The basic T3
link propagation delay simulator uses an IBM 3172
Interconnect Controller Model 2 with two HSSI adapters as shown in
transfer between the first and the second adapter
need not take place internally over the microchannel as shown in Fig.
2.0. A pair of DSUs and appropriate cable assemblies can be used to
connect the first HSSI adapter to the second adapter externally,
thereby bypassing the internal microchannel bus. Any protocol
exchange between HSSI adapters externally requires a pair of DSUs and
associated cable assemblies (Fig. 1.3).
The propagation delay simulator works as follows:
simulator has received an incoming packet or a data
block onto its input HSSI adapter (last bit in), the processor on