Browse Prior Art Database

S2 Line Sharing in NAND EEPROM

IP.com Disclosure Number: IPCOM000104606D
Original Publication Date: 1993-May-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Asano, H: AUTHOR

Abstract

This article describes S2 line sharing circuit for the two adjacent blocks in FLASH EEPROM to reduce the cell size.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

S2 Line Sharing in NAND EEPROM

      This article describes S2 line sharing circuit for the two
adjacent blocks in FLASH EEPROM to reduce the cell size.

      The figure shows how to share the select line S2 and G1 gate
between two adjacent blocks by mirroring the adjacent block
structure.  By setting S20 line ON, data will be outputted from D1
line with each related word line enabling (W1 to W8).  This design
enables to reduce one S2 line and one G1 gate per each two blocks.