Browse Prior Art Database

Gated Clock

IP.com Disclosure Number: IPCOM000104607D
Original Publication Date: 1993-May-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Nicholson, JO: AUTHOR

Abstract

The disclosed gated clock provides improved characteristics for clock generation circuits which have conditional requirements. Examples of this requirement include the use of a READY function in data transmission circuits, such as a bus interface. Typically, conditional clock gating introduces multiple logic delays in the production of a clock output and has a strong effect on maximum performance characteristics. This occurs when one considers worst case characteristics for both the transmitter and receiver. The gated clock circuit illustrated in the accompanying figure exhibits the following setup, hold and propagation delay characteristics, with subsequent improvements in minimum bus cycle time.

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Gated Clock

      The disclosed gated clock provides improved characteristics for
clock generation circuits which have conditional requirements.
Examples of this requirement include the use of a READY function in
data transmission circuits, such as a bus interface.  Typically,
conditional clock gating introduces multiple logic delays in the
production of a clock output and has a strong effect on maximum
performance characteristics.  This occurs when one considers worst
case characteristics for both the transmitter and receiver.  The
gated clock circuit illustrated in the accompanying figure exhibits
the following setup, hold and propagation delay characteristics, with
subsequent improvements in minimum bus cycle time.

    Clock propagation = one logic delay from source clock
    READY set up time = one logic delay two source clock
    READY hold time = one logic delay from source clock

      These characteristics have not been achieved with any previous
circuit designs and are essential to meeting architected bus
performance specifications for the MicroChannel* Architecture (MCA)
streaming data procedure.

      The circuit illustrated in the accompanying figure illustrates
clock circuitry for bus masters which implement the MicroChannel
Architecture (MCA) streaming data procedure.  This circuit provides a
conditional (gated) clock which is under the control of a slave
generated signal called CHRDYRTN.  The bus master provides a free
running bus c...