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Multisequencing a Single Instruction Stream - Generalizing the Level of Conditionality

IP.com Disclosure Number: IPCOM000104608D
Original Publication Date: 1993-May-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 211K

Publishing Venue

IBM

Related People

Ekanadham, K: AUTHOR [+3]

Abstract

The Level Of Conditionality (LC) of an instruction can be generalized to accommodate the full flexibility of alternate paths through the Z-CODE. Generalizing the definition of LC reflects a symmetrized view of handling alternate paths and allows the distinction between paths to be reflected in a distinction between LCs. Each path can be handled without partial LC as the LC unit already contains that path associated information. Splitting a pre-existing LC, creating the branchless LC does not impact the ZZT or OSC/PSC controls in a major fashion.

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Multisequencing a Single Instruction Stream - Generalizing the Level of Conditionality

      The  Level  Of  Conditionality (LC) of an instruction can be
generalized to accommodate the full flexibility of alternate paths
through the Z-CODE.  Generalizing the definition of LC reflects a
symmetrized view of handling alternate paths  and allows  the
distinction  between paths to be reflected in a distinction between
LCs.  Each path can be  handled  without partial  LC  as  the  LC
unit  already  contains  that path associated  information.
Splitting   a   pre-existing   LC, creating  the  branchless  LC
does  not  impact  the ZZT or OSC/PSC controls in a major fashion.

      Multisequencing a Single Instruction Stream (MSIS) is a
uniprocessor  organization  in  which  a  set  of processing elements
(PEs) working in concert execute Segments of   the   instruction
stream.  The  Segments  are  either P-Segments, normal uniprocessor
instruction stream portions, that are  processed  in  the  E-MODE  of
MSIS  and  produce Z-Segments,  or  the Z-Segments that are processed
in Z-MODE by MSIS.  The main difference between E-MODE  and  Z-MODE
is that  during  E-MODE  each  PE  sees all instructions in the
Segment and executes the ones that are assigned to  it,  but during
Z-MODE, a  PE only sees the instructions assigned to it.

      As all PEs see all instructions  in  E-MODE,  each  PE  can
create  the Z-CODE it will require to re-execute the Segment as a
Z-Segment, the Z-CODE being stored in the Z-CACHE,  and associated
with  instructions in the Z-CODE are S-LISTS and D-LISTS as
appropriate.  An S-LIST instructs the PE,  in  the Z-MODE,  that  one
or  more  of  the source registers in an instruction assigned to it
is  set  by  another  instruction that  is  executed  on  another PE,
an S-LIST is a receiving obligation.  The D-LIST instructs the PE in
the Z-MODE as to the names of PEs that require the values of the
register(s) that are being set by an instruction that is assigned to
it.  A D-LIST entry is a sending obligation.

      HISTORY OF LEVEL OF CONDITIONALITY - The design of MSIS had  to
be  provided  with  a  means  of recovery  from  a  BWG.  As  all  PE
proceed in parallel and operate asynchronously a means of  restoring
state  of  the machine at the point of a BWG was required.  All
instructions were  tagged  with  an indication at to the number of
branch instructions  that  preceded them so that no matter which PE
executed them and whatever cycle they  were  executed  on  a
concerted  recovery of the machine state at the proper point was
feasible.  It was found that in the case  of  serializers that  a
similar  recovery  was  required to the serializing instruction and
not merely to the next branch that  followed it.  The  LC
designation,  the level-of-conditionality, the aforementioned tag
assoc...