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Improved Sub-Micron MOS Technology

IP.com Disclosure Number: IPCOM000104609D
Original Publication Date: 1993-May-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 91K

Publishing Venue

IBM

Related People

Henley, WB: AUTHOR [+2]

Abstract

A significant problem in advanced MOSFET process technologies is the formation of the isolation regions. In previous technologies, the isolation regions were formed using the Local Oxidation (LOCOS) process. In the deep submicron region (<0.5 &mu.m minimum dimension), this process cannot be used because of the relatively large lateral bias associated with the LOCOS process. Consequently, the Shallow Trench Isolation (STI) process is used to form the isolation regions in the deep submicron region. However, this process is very complex and difficult because of the planarization steps involved.

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Improved Sub-Micron MOS Technology

      A significant problem in advanced MOSFET process technologies
is the formation of the isolation regions.  In previous technologies,
the isolation regions were formed using the Local Oxidation (LOCOS)
process.  In the deep submicron region (<0.5 &mu.m minimum
dimension), this process cannot be used because of the relatively
large lateral bias associated with the LOCOS process.  Consequently,
the Shallow Trench Isolation (STI) process is used to form the
isolation regions in the deep submicron region.  However, this
process is very complex and difficult because of the planarization
steps involved.

      This article describes a unique method to form both the
isolation and gate electrode regions that eliminates many of the
problems associated with the aforementioned techniques.

      The process flow begins after the formation of the N-well
regions.  A pad oxide of a thickness 20-50 nm using thermal
oxidation.  Polysilicon is deposited using Low Pressure Chemical
Vapor Deposition (LPCVD) at a thickness in the range of 200-400 nm.
The thickness of the polysilicon layer defines the isolation region
oxide thickness.  The polysilicon is patterned with the isolation
level photoresist pattern.  The photoresist pattern is transferred
into the polysilicon using Reactive Ion Etching (RIE) with a
chlorine-based process.  The etch process achieves a high etch
selectivity of polysilicon to oxide (>20:1).  The result after the
photoresist removal is presented in Fig. 1.  Next, the field implant
is performed.  The implant is optimized taking into account the lower
thermal cycle (non-LOCOS) associated with the disclosed process.  The
field implant is self-aligned to the active device region because the
polysilicon pattern covers what will become the active device region.
A layer of CVD oxide is depos...