Browse Prior Art Database

Queue Management with a Dual Port Memory

IP.com Disclosure Number: IPCOM000104616D
Original Publication Date: 1993-May-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 96K

Publishing Venue

IBM

Related People

Brezzo, B: AUTHOR [+3]

Abstract

Disclosed is a hardware management process of a set of queues of chained messages. It uses a dual port memory to hold the Queue Control Blocks (QCB) and allows to enqueue or dequeue a message within 2 machine cycles. It avoids any contention problem between the enqueuer and the dequeuer.

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This is the abbreviated version, containing approximately 52% of the total text.

Queue Management with a Dual Port Memory

      Disclosed is a hardware management process of a set of queues
of chained messages.  It uses a dual port memory to hold the Queue
Control Blocks (QCB) and allows to enqueue or dequeue a message
within 2 machine cycles.  It avoids any contention problem between
the enqueuer and the dequeuer.

      The enqueuer machine receives messages and loads them into a
data storage.  Then it dispatches them into different queues from
where they will be picked by the dequeuer machine, as shown in Fig.
1.

      In a given queue, messages are chained together by the enqueuer
thanks to a control field containing the next message address.

      Each message queue has an associated Queue Control Block
corresponding to an entry into a dual port memory.  It contains the
following fields:

o   Queue Status (E bit) : may be queue empty (E=1) or not (E=0)

o   Queue Head : address of the first message of the queue to be
    picked by the dequeuer

o   Queue Tail : address of the last message that has been put into
    the queue by the enqueuer.

      The contention problem to solve happens when there is only one
message into a given queue and the dequeuer wants to pick it up,
while the enqueuer is trying to enqueue a second message.

      A dual port memory allows to perform simultaneously during one
machine cycle two basic operations (read or write) by means of two
ports (PORT1 and PORT2).

      The access to this memory is controlled by an access manager.
This access manager is not only responsible of arbitrating between
the requesters and controlling the physical access to the memory (as
usually done) but also of all the operations relevant to an enqueue
or a dequeue order without intervention of the requester.

The advantages...