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Synchronizing Clock Frequency Memory Access for Asynchronous Entities

IP.com Disclosure Number: IPCOM000104620D
Original Publication Date: 1993-May-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 144K

Publishing Venue

IBM

Related People

Keung, TW: AUTHOR [+3]

Abstract

Described is an architectural logic implementation for personal computers (PCs) to ensure that the clock synchronization of the processor operation, in relation to the main memory, is compatible with the clock frequency of asynchronous entities that are interfaced to the PC.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 51% of the total text.

Synchronizing Clock Frequency Memory Access for Asynchronous Entities

      Described is an architectural logic implementation for personal
computers (PCs) to ensure that the clock synchronization of the
processor operation, in relation to the main memory, is compatible
with the clock frequency of asynchronous entities that are interfaced
to the PC.

      Typically, in order to obtain maximum performance in a central
electronics complex (CEC), it is necessary for asynchronous entities,
such as a processor and input/output (I/O) controllers to access the
main memory banks in such a way that the storage controller module
(SCM) is running in clock synchronous mode when the entity is
performing the access operations.  Often the processor and the I/O
entities may be running at different clock frequencies because the
entities are designed for maximization of their own performance.  In
prior art, designs where such that one entity would run
asynchronously with the SCM, which would then run synchronously with
the other entity.  The asynchronous entity would have to be
synchronized with the SCM at each memory access.  This caused a
synchronization penalty for every transfer.  The processor is
generally left to run asynchronously and the timings were usually
dictated by the architected I/O interface bus.  This made it
difficult to change the I/O controller frequency.

      The concept described herein provides a means whereby accesses
to the main memory are clock synchronized from an entity to the SCM.
Since no external synchronization logic is required, the processor
does not incur a synchronization penalty for each data transfer
cycle.

      Fig. 1 shows a block diagram of the synchronization concept.
The first entity 10 is running at frequency X and second entity 11 is
running at frequency Y.  Since both entity 10 and entity 11 have an
on-going need to periodically access memory banks by way of the SCM
hardware, two mechanisms for memory access are shown.  Entities 10
and 11 are connected to storage access finite state machines (FSMs)
12 and 13, respectively.  FSMs 12 and 13 connect to memory arbiter 14
where the decision is made as to which FSM will be in control of the
actual memory bank signal bus.  Synchronization logic and data path
communication module 15 is located between entities FSMs 12 and 13 to
provide the communication path between entities 10 and 11.  Dynamic
memory refresh can be controlled by either FSMs 12 or 13.

      Memory arbiter 14 is designed to run off either clock
frequencies of the entities.  It is designed to favor the entity with
the most stringent requirements for latency, such as the time
required to reach the first access.  Once the frequency has been
selected by arbiter 14, selector 16 is actuated to maintain stability
throughout the active memory access or refresh cycles.  Other
requirements may be imposed for performance reasons, but are not
required in order for this concept t...