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Self-Aligned Pocket Implantation Technology for Forming a Halo Type Device using Selective Tungsten Deposition

IP.com Disclosure Number: IPCOM000104621D
Original Publication Date: 1993-May-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 111K

Publishing Venue

IBM

Related People

Acovic, A: AUTHOR [+3]

Abstract

A technique to manufacture a localized self-aligned pocket implantation to form a "halo" type MOSFET device is presented. The localized pocket is formed by implantation using the gate electrode of the MOSFET device and a selectively deposited tungsten films as self-aligned masks. This technique provides high punch-through resistance, decreased Vt roll-off, high current capability device while maintaining low source/ drain junction capacitance and good device reliability compared to present techniques of forming a halo type FET device.

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Self-Aligned Pocket Implantation Technology for Forming a Halo Type Device using Selective Tungsten Deposition

      A technique to manufacture a localized self-aligned pocket
implantation to form a "halo" type MOSFET device is presented.  The
localized pocket is formed by implantation using the gate electrode
of the MOSFET device and a selectively deposited tungsten films as
self-aligned masks.  This technique provides  high  punch-through
resistance, decreased  Vt roll-off, high current capability device
while maintaining low source/ drain junction capacitance and  good
device reliability compared to present techniques of forming a halo
type FET device.

      To  decrease  the short-channel effects in MOSFETs, the
substrate doping has to be raised.  However,  this  increases the
source  and  drain  junction capacitance and lowers the device
current  drive.  This  high  capacitance  and  lower current result
in reduced circuit speed, cancelling partially the beneficial effects
of channel  shortening.  By increasing  the  substrate  doping  in
the source and drain regions near the channel while keeping it as low
as possible in the channel region,  we  can  improve  the
short-channel behavior   of   the   MOSFET  device  without
significantly affecting its drain junction capacitance and  current
drive capability.

      One  solution to this problem is described in [1].  A standard
CMOS  process  with  SALICIDED source/drain junctions  is  utilized.
The nitride spacer formed before source drain salicidation is removed
and Boron is  implanted (in  n-channel  devices)  obliquely  through
this hole.  The TiSi sub 2 prevents the doping from extending around
the junction, while the angle implant allows the doping to reach
below  the  channel.  However,  this  process,  although  it achieves
the desirable channel  doping  below  the  channel, forbids to remove
or anneal the damage to the gate oxide due to the oblique
implantation, because:

1.  The quality of the TiSi sub 2 layer is adversely affected by an
    anneal at high temperature (>800ºC) which is required to
    repair damage caused to the  gate  oxide  during  the "halo"
    implantation.

2.  The  thermal  cycle  required  to anneal the gate damage
    described in point 1 will result in deeper source  drain
    junctions  as  well  as  a deeper halo region.  This will result
    in poor short channel device characteristics.

3.  TiSi sub 2 cannot withstand an HF dip which might be required
    before the anneal in point 1.  This is because TiSi sub 2 is
    etched far faster than the oxide.

This  paper  describes  a  new technique to solve these problems.

      Proposed is the use of a standard CMOS process  with  or
without  silicide.  The  halo  implant  is  formed  prior to
source/d...