Browse Prior Art Database

Method for Fetching after Branches in a Superscalar Microprocessor

IP.com Disclosure Number: IPCOM000104630D
Original Publication Date: 1993-May-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Karim, FO: AUTHOR [+3]

Abstract

A method is described for fetching instructions after a branch is encountered in a superscalar microprocessor.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 74% of the total text.

Method for Fetching after Branches in a Superscalar Microprocessor

      A method is described for fetching instructions after a branch
is encountered in a superscalar microprocessor.

      In a superscalar microprocessor, branch penalties can be very
costly.  A penalty of 3 cycles represents up to 12 instructions worth
of delay (in an example machine that fetches 4 instructions per
cycle).

      The basic strategy is called BST(S).  B indicates the cycle
where the branch instruction was fetched.  S indicates the following
cycle, where the next 4 sequential instructions are target cycle,
where the target instructions are fetched.  (S) indicates the next
cycle, where the next 4 sequential instructions are fetched and held
until the branch resolves.

      With this method, branch penalties can be greatly reduced.  In
the following figures, pipeline charts are shown for an example
superscaler machine with 4-instruction fetch and 2 fixed-point units.

      Fig. 1 shows branch penalties for a superscalar machine with no
branch prediction.  A penalty of 3 cycles always results.

      Figs. 2 and 3 show branch penalties for a typical superscaler
machine with branch prediction only.  As the chart shows, for
correctly predicted branches the penalties are 0 cycles for not taken
and 1 cycle for taken.  For mispredicted branches the penalty is 3
cycles.  Even with a very large, costly prediction buffer, the branch
prediction accuracy is unlikely to...