Browse Prior Art Database

Segment Register Mechanism for Mapping Input/Output Facilities of a Processor Complex

IP.com Disclosure Number: IPCOM000104635D
Original Publication Date: 1993-May-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Mathis, JR: AUTHOR [+2]

Abstract

In a processor complex which provides virtual address capability, a hardware facility known as a segment register is utilized to map the effective address referenced by the instruction to the virtual address of the system. The segment register mechanism may be utilized to integrate access to the Input/Output subsystem into the virtual address structure of the processor, provide a uniform mechanism to access storage and Input/Output, and an address extension that may be utilized for either address or control purposes.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 82% of the total text.

Segment Register Mechanism for Mapping Input/Output Facilities of a Processor Complex

      In a processor complex which provides virtual address
capability, a hardware facility known as a segment register is
utilized to map the effective address referenced by the instruction
to the virtual address of the system.  The segment register mechanism
may be utilized to integrate access to the Input/Output subsystem
into the virtual address structure of the processor, provide a
uniform mechanism to access storage and Input/Output, and an address
extension that may be utilized for either address or control
purposes.

      One example of this segment register mechanism is the 32 bit
register depicted in the accompanying drawing.  As illustrated, the
first bit is utilized to indicate the type and may be utilized to
differentiate between L/S references to main storage and
Input/Output.  Next, a single bit key field is utilized to define the
privilege state of the code that is accessing the Input/Output
subsystem.  A single bit escape field is utilized to define
additional Input/Output segment register formats for future
expansions and a single reserved bit field is also provided for
future expansion.

      Next, an 8 bit field is utilized to provide the Bus Unit ID
(BUID) to provide the address of the referenced channel.  The final
twenty bits of the segment register mechanism is utilized to provide
a specific adapter (channel) with an additional twenty bits of
addr...