Browse Prior Art Database

Retriggerable Single-Shot Pulse Generator with a Digital Delay

IP.com Disclosure Number: IPCOM000104645D
Original Publication Date: 1993-May-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 70K

Publishing Venue

IBM

Related People

Dhong, SH: AUTHOR [+3]

Abstract

Disclosed is a new retriggerable single-shot pulse generator with a digital delay. Instead of using an RC network with a comparator as in the prior-art, the circuit uses a NAND circuit as a delay line. Consequently, the circuit tracks better with overall process variations and consumes less power because of its digital nature.

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Retriggerable Single-Shot Pulse Generator with a Digital Delay

      Disclosed is a new retriggerable single-shot pulse generator
with a digital delay.  Instead of using an RC network with a
comparator as in the prior-art, the circuit uses a NAND circuit as a
delay line.  Consequently, the circuit tracks better with overall
process variations and consumes less power because of its digital
nature.

      A commonly used retriggerable single-shot pulse generator
comprises an RC delay and a comparator to generator to single-shot
pulses.  Retriggering of the circuit before the completion of a
single-shot pulse is achieved by discharging the capacitor by an
input pulse.  However, in CMOS digital applications implementation of
the RC delay and comparator is quite often complicated because of
process limitations.  A new retriggerable single-shot pulse generator
is based on a NAND circuit chain to generate a pulse delay instead of
a RC delay line.  The NAND circuit chain is reset when the generator
is retriggered.  Since the circuit uses a digital delay without any
comparator which consumes DC power, it is more compatible with
low-power digital CMOS chips than the prior-art circuit.

      The circuit is schematically shown in the figure and its
operation is described in the steps below.

1.  When the input ATDSUM is high, the node N is low and forces the
    node M high.  RESETDLY and RESETDLYB are low and high,
    respectively.  We will assume that the node Q1 is low.  (This
    assumption holds true as we see later because the RESETDLY was
    pulsed to high, setting nodes and Q1 and QB1 low and high,
  ...