Browse Prior Art Database

DMA Interface for a High Speed Decompression Device

IP.com Disclosure Number: IPCOM000104662D
Original Publication Date: 1993-May-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 103K

Publishing Venue

IBM

Related People

Dahanayaka, SD: AUTHOR [+2]

Abstract

This design provides a high speed DMA interface from an attached multiple buffer memory to a high performance compression/decompression device and another DMA path back to another programmable location in the attached memory. This design pipelines data bursts on the interface bus and provides several hardware assists to aid performance.

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This is the abbreviated version, containing approximately 54% of the total text.

DMA Interface for a High Speed Decompression Device

      This design provides a high speed DMA interface from an
attached multiple buffer memory to a high performance
compression/decompression device and another DMA path back to another
programmable location in the attached memory.  This design pipelines
data bursts on the interface bus and provides several hardware
assists to aid performance.

      This design provides two DMA devices to pipeline compressed
data into the decompression device.  Two additional DMA devices
pipeline data out of the decompression device.  Each DMA device
attaches to a high speed memory interface bus on one end.  This high
speed memory interface bus is also attached to a microprocessor.

      The high speed memory interface bus has three DMA masters and a
DMA slave (the microprocessor) attached as well as providing an
interface to several megabytes of DRAM.  All compressed data is
transferred into the attached memory from a channel attachment
device.  The input data is split up into buffers which also contain
various control commands.  This results in compressed data that is
split into a series of buffers of various lengths and which each
start on arbitrary byte boundaries in relocatable areas of memory.

The decompression device requires that the compressed data be
provided 16 bits at a time.

      In our application, the high speed memory interface bus is a 32
bit wide bus.  In addition, the decompression device does...