Browse Prior Art Database

Alternate S1 Line in NAND Type Flash EEPROM

IP.com Disclosure Number: IPCOM000104663D
Original Publication Date: 1993-May-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Asano, H: AUTHOR

Abstract

This article describes the alternate select gate circuit which enables the read operation when the select gate shorts in NAND FLASH EEPROM.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Alternate S1 Line in NAND Type Flash EEPROM

      This article describes the alternate select gate circuit which
enables the read operation when the select gate shorts in NAND FLASH
EEPROM.

      The major failure in NAND FLASH EEPROM is the select gate
shorts which disables the read and write operation on the NAND cell
block selected by that gate.  Fig. 1 shows the prior circuit.  NAND
cell block can be read by enabling S1 and S2 line.  The data of each
cell can be read by enabling W1 to W4 one by one.

      Fig. 2 shows the additional select circuits for the alternate
read path.  In addition to the select gate G10, G20 gate is added to
connect to the adjacent block.  G0 and G1 gate use FET.  G00 uses FET
but G10 uses EEPROM.  In the normal operation the voltage (V1)
applied to S20 enables G10 ON state.  V1 does not make G20 ON state.
If the error is detected in this block, G10 state should be changed
by writing "1" in G10.  After that, by applying the voltage V2
(N2>V1) on S20 which enables G20 ON but G10 OFF, check the data on D1
by G01 ON.  If the D1 is 0, G00 is short state, and D1 is 1, G00 is
open state.

      For the failure of G00 short, the data of C1 to C4 can be read
through G20 and G01 by enabling W1 to W4 in sequence.