Browse Prior Art Database

Self-Timed Logic Using Current Sensing Completion Detection

IP.com Disclosure Number: IPCOM000104665D
Original Publication Date: 1993-May-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 167K

Publishing Venue

IBM

Related People

Dean, ME: AUTHOR

Abstract

Described is a circuit implementation utilizing current sensing completion detection (CSCD) techniques as a means of implementing Boolean functions in self-timed logic. The CSCD technique allows self-timed circuits to be designed using single-rail variable encoding, as compared with dual-rail encoding methods, so as to reduce the number of signal wires and transistors.

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Self-Timed Logic Using Current Sensing Completion Detection

      Described is a circuit implementation utilizing current sensing
completion detection (CSCD) techniques as a means of implementing
Boolean functions in self-timed logic.  The CSCD technique allows
self-timed circuits to be designed using single-rail variable
encoding, as compared with dual-rail encoding methods, so as to
reduce the number of signal wires and transistors.

      Typically, self-timed logic provides a method for designing
asynchronous logic circuits such that their correct behavior is
independent of the speed of their components or signal wire delays.
In prior art, dual-rail signalling was used where every logical
variable was encoded using two signal wires, called an encoding pair.
4-phase dual-rail utilized three logical values; 0, 1, and invalid.
The protocol for 4-phase dual-rail signalling required that the
logical variable return to the invalid state after taking a 0 or 1
value.  The invalid logic values served as spacer tokens which
separated the valid tokens in the data stream so as to provide for
the self-timed logic to detect the completion of a logic function for
each data token.  Several methods of the dual-rail logic concept have
been used, however, each method sacrifices silicon area and causes
function block delays.  In contrast, the concept described herein
utilizes CSCD techniques in single-rail variable encoding which can
reduce the number of signal wires and transistors used in a
self-timed Boolean function implementation by up to 50%.  This is
accomplished due to the reduction in parasitic capacitance, the
removal of spacer tokens in the data stream and computation state
locality for consecutive data variables, and the overall improvement
in performance over the dual-rail technique.

      The CSCD uses the variation in current flow inherent to CMOS
logic functions during processing to detect the completion of a given
operation.  Since a CSCD implementation does not directly use a
signal wire variation to detect the completion, single-rail variable
encoding, similar to synchronous encoding, is used.  The same Boolean
function blocks used in a synchronous design can be used in an
equivalent CSCD implementation.  The CSCD function blocks need not be
hazard free as in most self-timed dual-rail logic structures.
Therefore, a self-timed logic structure implemented using CSCD
requires approximately half the number of signal wires and gate
transistors over an equivalent dual-rail structure.  Operational
efficiency is enhanced over 4-phase dual-rail encoding methods due to
the elimination of spacer tokens between valid data tokens.  CSCD
logic structures have the ability to take advantage of computation
state locality within the data stream.  Computation state locality
refers to the similarities between a functions final processing
present variable's computation state is to the previous operation
within a given function block, t...