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Space Saving Design for Reporting Error Correcting Code Errors

IP.com Disclosure Number: IPCOM000104669D
Original Publication Date: 1993-May-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

East, RE: AUTHOR [+2]

Abstract

A ECC error reporting function is disclosed which uses existing logic to fit the design onto a single chip. The RIOS Single Chip processor (RSC) implements an ECC error reporting function with six 32-bit read only registers and one 32-bit write register. Instead of utilizing discrete registers in the RSC for ECC erro registers, a RAM is used. Random logic that is normally used between register elements is replaced by a microcoded sequencer which is already in the design to aid DMA activity. The sequencer is used to access the register elements in t RAM. Additional logic to interface with the memory subsystem is kept to a minimum via a common interface to the microcoded sequencer.

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Space Saving Design for Reporting Error Correcting Code Errors

      A ECC error reporting function is disclosed which uses existing
logic to fit the design onto a single chip.  The RIOS Single Chip
processor (RSC) implements an ECC error reporting function with six
32-bit read only registers and one 32-bit write register.  Instead of
utilizing discrete registers in the RSC for ECC erro registers, a RAM
is used.  Random logic that is normally used between register
elements is replaced by a microcoded sequencer which is already in
the design to aid DMA activity.  The sequencer is used to access the
register elements in t RAM.  Additional logic to interface with the
memory subsystem is kept to a minimum via a common interface to the
microcoded sequencer.

      The microcoded sequencer is used to read the address of the
error and the syndrom associated with the data.  Memory loads are
performed on a sixty-four bit double word that has an eight bit
syndrom.  Single bit errors are corrected they are read from memory
which incurs a one cycle penalty.  Double bit errors are detected but
not corrected.  The sequencer distinguishes what type of error
occurred via reading a status register in the ECC logic.  Reading the
status reg permits the microcode to sort out posting of errors into
three pairs of status a associated address registers such as single
bit errors, double bit errors not fr DMA, and DMA ECC.  After posting
of the error, no further posting is perfor...