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Multisequencing a Single Instruction Stream Schedule Based on Limited Branch Exposure

IP.com Disclosure Number: IPCOM000104680D
Original Publication Date: 1993-May-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 137K

Publishing Venue

IBM

Related People

Ekanadham, K: AUTHOR [+3]

Abstract

The scheduling of instructions based on the timing of the inputs leads to a large span of sequence numbers that are decoded on the same cycle. This span can be limited parametrically by employing a formula due to [*]. The inclusion of the r-th largest branch resolution time in the algorithm which selects the decode slot for the i-th instruction limits the span between instructions that are decoded on the same cycle in a meaningful way. The approach recognizes that unresolved branches rather than any fixed number of instructions is the real measure of span as all instructions between branch points have the same architectural execution commitment no matter how many there are of them.

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Multisequencing a Single Instruction Stream Schedule Based on Limited Branch Exposure

      The scheduling of instructions based on the timing of the
inputs leads to a large span of sequence numbers that are decoded on
the same cycle.  This span can be limited parametrically by employing
a formula due to [*].  The inclusion of the r-th largest branch
resolution time in the algorithm which selects the decode slot for
the i-th instruction limits the span between instructions that are
decoded on the same cycle in a meaningful way.  The approach
recognizes that unresolved branches rather than any fixed number of
instructions is the real measure of span as all instructions between
branch points have the same architectural execution commitment no
matter how many there are of them.

      MSIS is a uniprocessor organization in which a set of
processing elements (PE) working in concert execute Segments of the
instruction stream.  The Segments are either P-Segments, normal
uniprocessor instruction stream portions, that are processed in the
E-MODE of MSIS and produce Z-Segments, or the Z-Segments that are
processed in Z-MODE by MSIS.  The main difference between E-MODE and
Z-MODE is that during E-MODE each PE sees all instructions in the
Segment and executes the ones that are assigned to it, but during
Z-MODE, a PE only sees the instructions assigned to it.

      As all PEs see all instructions in E-MODE, each PE can create
the Z-CODE it will require to re-execute the Segment as a Z-Segment,
the Z-CODE being stored in the Z-CACHE, and associated with
instructions in the Z-CODE are S-LISTS and D-LISTS as appropriate.
An S-LIST instructs the PE, in the Z-MODE, that one or more of the
source registers in an instruction assigned to it is set by another
instruction that is executed on another PE, an S-LIST is a receiving
obligation.   The D-LIST instructs the PE in the Z-MODE as to the
names of PEs that require the values of the register(s) that are
being set by an instruction that is assigned to it.  A D-LIST entry
is sending obligation.

      The set of instructions assigned to a single PE, can be further
delineated as THREADS.  A THREAD is a sequence of instructions in the
original conceptual order and a Thread is associated with a register
file which is either real or virtual.  There is no sending or
receiving obligations between instructions with a THREAD and the
THREAD is the smallest unit of aggregation of instructions from a
SEGMENT.

      Individual instructions while executing carry an indication as
to which SEGMENT, DECODER, and THREAD to which they belong.  The
information concerning the DECODER and THREAD is derived from the
Z-CODE itself.  The SEGMENT index is assigned sequentially at each
SEGMENT SWITCH.  Segment switches occur at points in the code where
the Z-SEGMENT terminates or where a Branch Wrong Guess has been
detected.

      MSIS HEM is a High-End Machine design that uses multiple
decoders wi...