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Improvement in Short-Channel-Effects in NMOS by Boron Co-Implantation into Source/Drain Regions

IP.com Disclosure Number: IPCOM000104686D
Original Publication Date: 1993-May-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 86K

Publishing Venue

IBM

Related People

Davari, B: AUTHOR [+3]

Abstract

An improved FET structure is disclosed in which the short-channel threshold lowering effects are minimal due to the use of an extra processing step in which high levels of the background doping type are added to the opposite doping type in the source and drain region.

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Improvement in Short-Channel-Effects in NMOS by Boron Co-Implantation into Source/Drain Regions

      An improved FET structure is disclosed in which the
short-channel threshold lowering effects are minimal due to the use
of an extra processing step in which high levels of the background
doping type are added to the opposite doping type in the source and
drain region.

      The roll off of Vt in Si MOSFETs at gate lengths of <=
0.3 &mu.  is a serious problem for the present  and future generation
CMOS based Si ICs.  The inherent contributors to SCE in a Si MOSFET
are the two dimensional potential  distribution  and  high electric
fields.  In NMOS devices fabricated on a B-doped Si substrate, it is
believed that the B redistribution in the channel region during
processing contributes further to SCE.  The redistribution occurs
because source/drain regions of an NMOS contain  a high concentration
of ion implanted As, and B from the substrate segregates to the
As-rich region during post-implantation annealing.  B segregation
into an As-implanted region during annealing is  demonstrated  in  a
control  experiment  where  different doses of BF&sub2.  were
co-implanted at 175 keV into As-implanted (30 keV) Si (Fig. 1).  A
similar segregation of B from the channel of a NMOS into As-implanted
source/drain regions  is  expected  during processing which would
exacerbate SCE in an NMOS.

      This  invention  describes a method which can alleviate SCE by
incorporating B into and around source/drain  regions of an NMOS by
ion...