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Circuit for Establishing Test Modes

IP.com Disclosure Number: IPCOM000104692D
Original Publication Date: 1993-May-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Clarke, GL: AUTHOR [+4]

Abstract

Disclosed is a circuit used to provide for an additional test mode within an integrated circuit device without requiring the use of an additional test pin. The signal levels of two test pins are compared to determine the test mode.

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Circuit for Establishing Test Modes

      Disclosed is a circuit used to provide for an additional test
mode within an integrated circuit device without requiring the use of
an additional test pin.  The signal levels of two test pins are
compared to determine the test mode.

      An I/O controller circuit module uses two test pins, to which
-TEST INHIBIT and -CLOCK ISOLATE signals are respectively applied, in
conjunction with a conventional LSSD (Level Sensitive Scan Design)
design.  In the LSSD test mode, the -TEST INHIBIT signal is always
low.  The -CLOCK ISOLATE signal is only low when the A Clock is used
for shifting data through a scan string.  Both these signals are high
in the functional mode.  The -CLOCK ISOLATE signal is used
additionally, when its level is pulled low, to place the circuit
module in an ICT (In Circuit Test) mode, in which each input drives
one or more outputs, with its inverted level bypassing functional
circuitry.  Most functional outputs are changed into bi-directional
pins, which can be used as inputs in the ICT mode.

      As shown in the figure, the -CLOCK ISOLATE signal is provided
as an input to an input buffer 1, while the -TEST INHIBIT signal is
provided as an input to input buffer 2.  The enable signals generated
by this circuit determine the mode of operation of the circuit
module.

      When both of these signals are high, the +SYSTEM CLOCKS ENABLE
signal is generated through OR gate 3, and since the inverted o...