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Noise Reduction During Test by Transceiver Threshold Voltage

IP.com Disclosure Number: IPCOM000104696D
Original Publication Date: 1993-May-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 71K

Publishing Venue

IBM

Related People

McWilliam, B: AUTHOR [+2]

Abstract

Disclosed is a method for reducing noise during integrated circuit testing. This is accomplished by altering the voltage that Common I/O are pulled to by the tester such that the high-gain region of the receiver circuitry is avoided.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Noise Reduction During Test by Transceiver Threshold Voltage

      Disclosed is a method for reducing noise during integrated
circuit testing.  This is accomplished by altering the voltage that
Common I/O are pulled to by the tester such that the high-gain region
of the receiver circuitry is avoided.

      Most noise generated during IC testing is caused by switching
of the off chip drivers (OCDs).  This is due to the fact that these
transistors are typically the largest within the circuit and thus
most likely to generate the largest changes of current (di/dt).
Additionally, the off chip drivers set a higher inductive load than
internal circuitry.  The close proximity of OCDs and OCRs can also
provide a positive feedback loop for circuit switching.
Specifically, OCD switching (di/dt) creates a voltage delta equal to
Ldi/dt.  This noise is then coupled back through the OCRs, which, in
turn creates more switching internally.  Ultimately, this switching
propagates to the OCDs, which switch again, repeating the loop.  This
then creates an oscillation which will, most likely, cause the IC to
fail during test.

      While steps can be taken to avoid this coupling of noise back
into the standard OCR, prior to this invention, no method was known
for the case of transceivers (common I/O).  In fact, the existing pin
conditioning for this circuitry inadvertently represented the worst
case loading for these transistors.  Common I/O (CIOs) are
essentially OCDs feeding OCRs.  To permit the CIO to receive signals
(act as an OCR), the OCD is placed in the high impedance state.  For
99%+ of the test patterns, the OCR is in this high impedance state
and NO signal is being driven into the chip by the tester.  In such
cases, tester pin electronics is programmed so th...