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Space-Saving Design for External Interrupts

IP.com Disclosure Number: IPCOM000104697D
Original Publication Date: 1993-May-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

East, R: AUTHOR [+2]

Abstract

External interrupt functions in a single chip processor are typically implemented utilizing nine read/write registers and one read only register. From a physcial design perspective, the most dense structures within a processor are arrays. Instead of utilizing discrete registers in a single chip processor for interrupt registers, a Random Access Memory (RAM) may be utilized instead. Random logic that is normally utilized between register elements is replaced by a microcoded sequencer to access the register elements in a Random Access Memory. This sequencer is already present within the processor design for aid in Direct Memory Access (DMA) activity.

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Space-Saving Design for External Interrupts

      External interrupt functions in a single chip processor are
typically implemented utilizing nine read/write registers and one
read only register.  From a physcial design perspective, the most
dense structures within a processor are arrays.  Instead of utilizing
discrete registers in a single chip processor for interrupt
registers, a Random Access Memory (RAM) may be utilized instead.
Random logic that is normally utilized between register elements is
replaced by a microcoded sequencer to access the register elements in
a Random Access Memory.  This sequencer is already present within the
processor design for aid in Direct Memory Access (DMA) activity.
Additional logic for acceptance of interrupts is kept to a minimum by
utilizing the microcoded sequencer to preload a hardware register and
the logical AND of three register contents.  The disclosed design
utilizes a microcoded sequencer to read the status of the interrupts
on external I/O pins.  The sequencer also performs the logic function
to mask out interrupts which are not enabled by ANDing the external
interrupts with the contents of the Interrupt Enable Register (IER)
which is located in the sequencer's private Random Access Memory.
Interrupts may be masked out by the External Interrupt Mask.  The
microcoded sequencer ANDs bits 0 through 15 of the External Interrupt
Mask 0 with the hardware interrupts from the I/O pins.  The results
of the two masking operations is then ORed via the sequencer with
existing interrupts in the Interrupt Summ...